Semiconductor epitaxy bordering isolation structure

1. A method, comprising:

providing a structure having a semiconductor substrate with an active region, the active region having source and drain regions, the structure further having an isolation structure at least partially embedded in the semiconductor substrate;

etching a trench in one of the source and drain regions, the trench exposing a portion of the isolation structure;

forming a first semiconductor layer in the trench;

forming a second semiconductor layer over the first semiconductor layer;

changing a crystalline facet orientation of a portion of a surface of the second semiconductor layer by an etching process; and

after the changing of the crystalline facet orientation, forming a third semiconductor layer over the second semiconductor layer.

2. The method of claim 1 , wherein each of the second and third semiconductor layers is in direct contact with the isolation structure, wherein a first side surface of the second semiconductor layer is oriented in crystalline plane (1, 1, 1), and a second side surface of the second semiconductor layer is oriented in one of crystalline planes of {3, 1, 1}, {5, 1, 1}, {7, 1, 1}, and {9, 1, 1}.

3. The method of claim 1 , further comprising:

forming an inter-layer dielectric (ILD) layer over the active region and the isolation structure; and

forming a conductive feature embedded in the ILD layer and contacting the third semiconductor layer.

4. The method of claim 1 , wherein the first semiconductor layer comprises silicon germanium doped with a p-type dopant, and each of the second and third semiconductor layers comprises silicon doped with the p-type dopant.

5. The method of claim 1 , wherein the etching process uses a chemical including hydrogen chloride (HCl).

6. A method, comprising:

providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region;

etching a trench in one of the source and drain regions, wherein the trench exposes a portion of a sidewall of the isolation structure;

epitaxially growing a first semiconductor layer in the trench;

epitaxially growing a second semiconductor layer over the first semiconductor layer;

changing a crystalline facet orientation of a portion of a top surface of the second semiconductor layer by an etching process; and

after the changing of the crystalline facet orientation, epitaxially growing a third semiconductor layer over the second semiconductor layer.

7. The method of claim 6 , wherein before the changing of the crystalline facet orientation, the portion of the top surface of the second semiconductor layer is in crystalline plane (1, 1, 1), and after the changing of the crystalline facet orientation, the portion of the top surface of the second semiconductor layer is in one of crystalline planes of: (3, 1, 1), (5, 1, 1), (7, 1, 1), (9, 1, 1), (1, 3, 1), (1, 5, 1), (1, 7, 1), (1, 9, 1), (1, 1, 3), (1, 1, 5), (1, 1, 7), and (1, 1, 9).

8. The method of claim 6 , further comprising:

forming an inter-layer dielectric (ILD) layer over the third semiconductor layer; and

forming a contact feature in the ILD layer and contacting the third semiconductor layer.

9. The method of claim 6 , wherein the first and second semiconductor layers collectively partially fill the trench.

10. The method of claim 6 , wherein the etching process uses a chemical including hydrogen chloride (HCl).

11. The method of claim 6 , wherein the first semiconductor layer includes silicon germanium.

12. The method of claim 11 , further comprising:

doping the first semiconductor layer with a p-type dopant before the epitaxially growing of the second semiconductor layer.

13. The method of claim 12 , wherein each of the second and third semiconductor layers includes silicon.

14. The method of claim 13 , further comprising:

doping the third semiconductor layer with the p-type dopant.

15. A method, comprising:

providing a semiconductor structure having an active region and an isolation structure adjacent to the active region, the active region having source and drain regions sandwiching a channel region for a transistor, the semiconductor structure further having a gate structure over the channel region;

etching a trench in one of the source and drain regions, wherein a first side surface of the trench is a portion of a sidewall of the isolation structure, and a second side surface of the trench is oriented in crystalline plane (1, 1, 1);

epitaxially growing a first semiconductor layer in the trench;

epitaxially growing a second semiconductor layer over the first semiconductor layer, wherein a top surface of the second semiconductor layer is oriented in crystalline plane (1, 1, 1);

etching the second semiconductor layer, thereby changing crystalline facet orientation of a portion of the top surface of the second semiconductor layer; and

after the etching of the second semiconductor layer, epitaxially growing a third semiconductor layer over the second semiconductor layer.

16. The method of claim 15 , wherein after the etching of the second semiconductor layer, the crystalline facet orientation of the portion of the top surface of the second semiconductor layer is in one of crystalline planes of: {3, 1, 1}, {5, 1, 1}, {7, 1, 1}, and {9, 1, 1}.

17. The method of claim 15 , wherein the etching of the second semiconductor layer uses a chemical including hydrogen chloride (HCl).

18. The method of claim 15 , wherein the first semiconductor layer comprises silicon doped with an n-type dopant.

19. The method of claim 15 , wherein the first semiconductor layer comprises silicon germanium doped with boron.

20. The method of claim 19 , wherein each of the second and third semiconductor layers comprises silicon doped with boron.