Methods and apparatus for voltage and current calibration
A calibration circuit may comprise a negative pack terminal, an intermediate node, and a first protection IC coupled to a first transistor. The first transistor may be coupled between the negative pack terminal and the intermediate node. The calibration circuit may comprise a second protection IC coupled in parallel with the first protection IC and further coupled to a second transistor. A power source may be coupled in parallel with the first and second protection ICs, and a current source may be coupled between the negative pack terminal and the intermediate node, wherein the intermediate node is positioned between the first transistor and the second transistor, and the power source is configured to provide a current to the first protection IC through a first current loop.
1. A calibration circuit, comprising:
a battery pack comprising a negative pack terminal; and
an intermediate node;
a first protection IC coupled to a first transistor, wherein the first transistor is coupled between the negative pack terminal and the intermediate node;
a second protection IC coupled in parallel with the first protection IC and coupled to a second transistor;
a power source adapted to be coupled in parallel with the first and second protection ICs; and
a current source adapted to be coupled between the negative pack terminal and the intermediate node;
wherein:
the intermediate node is positioned between the first transistor and the second transistor; and
the power source is configured to provide a current to the first protection IC through a first current loop.
2. The calibration circuit according to claim 1 , wherein the first current loop comprises the second transistor.
3. The calibration circuit according to claim 1 , wherein the second transistor is configured to select between the first current loop and a second current loop configured to bypass the second transistor.
4. The calibration circuit according to claim 1 , wherein the first current loop is configured to generate a first voltage across a first terminal and a second terminal of the first protection IC.
5. The calibration circuit according to claim 1 , wherein the current source is configured to generate a current source loop, wherein the current source loop flows through the first transistor.
6. The calibration circuit according to claim 5 , wherein the current source comprises a selectable bypass loop to restrict the flow of the third current loop.
7. The calibration circuit according to claim 1 , further comprising a pulse generator configured to provide a test signal to the protection IC being calibrated.
8. A method for performing calibration of a first protection IC coupled in parallel with a second protection IC and a power source, wherein the first protection IC is coupled to a first transistor and the second protection IC is coupled to a second transistor, comprising:
calibrating the second protection IC; and
calibrating the first protection IC after the second protection IC has been calibrated, comprising:
activating the power source to generate a first current;
activating the second transistor to form the first current into a first current loop through the second transistor; and
generating a second current with a current source to form a second current loop, wherein the second current flows through the first transistor.
9. The method for performing calibration according to claim 8 , wherein calibrating the second protection IC comprises selectively coupling the power source to the second protection IC through one of a current calibration loop and a voltage calibration loop.
10. The method for performing calibration according to claim 9 , wherein the current calibration loop comprises a sense resistor coupled between the power source and a second terminal of the second protection IC.
11. The method for performing calibration according to claim 8 , wherein calibrating the second protection IC comprises selectively coupling the current source to a bypass loop, wherein the bypass loop bypasses the second protection IC.
12. The method for performing calibration according to claim 11 , wherein calibrating the first protection IC comprises applying a test signal from a pulse generator coupled to the first protection IC when the current source is coupled to the bypass loop.
13. A calibration system, comprising:
a battery pack comprising:
a positive pack terminal;
a negative pack terminal;
an intermediate node;
a first protection IC coupled to the positive pack terminal and a first transistor, wherein the first transistor is coupled between the negative pack terminal and the intermediate node;
a second protection IC coupled in parallel with the first protection IC and coupled to a second transistor, wherein the second transistor is coupled between the intermediate node and the negative pack terminal;
a power supply coupled between the positive and negative pack terminal; and
a current source coupled between the negative pack terminal and the intermediate node;
wherein:
the power source is capable of delivering a current to the first protection IC through a first current loop; and
the first current loop comprises the second transistor.
14. The calibration circuit according to claim 13 , wherein the second transistor is configured to select between the first current loop and a second current loop configured to bypass the second transistor.
15. The calibration circuit according to claim 13 , wherein the first current loop is configured to generate a first voltage across a first terminal and a second terminal of the first protection IC.
16. The calibration circuit according to claim 1 , wherein the current source is configured to generate a current source loop, wherein the current source loop flows through the first transistor.
17. The calibration circuit according to claim 5 , wherein the current source comprises a selectable bypass loop to restrict the flow of the third current loop.
18. The calibration circuit according to claim 1 , further comprising a pulse generator configured to provide a test signal to the protection IC being calibrated.