Thermal management for photonic integrated circuits
Embodiments of the invention describe apparatuses, systems, and methods of thermal management for photonic integrated circuits (PICs). Embodiments include a first device and a second device comprising including waveguides, wherein the first and second devices have different thermal operating conditions. A first region is adjacent to a waveguide of the first device, wherein its optical mode is to be substantially confined by the first region, and wherein the first region has a first thermal conductivity to dissipate heat based on the thermal operating condition of the first device. A second region is adjacent to a waveguide of the second device, wherein its optical mode is to be substantially confined by the second region, and wherein the second region has a second thermal conductivity to dissipate heat based on the thermal operating condition of the second device. In some embodiments, thermal cross talk is reduced without significantly affecting optical performance.
1. A layered photonic integrated circuit, comprising:
a silicon layer having a top side that defines a plane extending in a lateral direction;
a first waveguide positioned on the top side of the silicon layer;
a first region positioned on a bottom side of the silicon layer and laterally aligned with the first waveguide, the first region having a first thermal conductivity, the first region being a buried oxide layer;
a second waveguide positioned on the top side of the silicon layer and laterally offset from the first waveguide; and
a second region positioned on the bottom side of the silicon layer and laterally aligned with the second waveguide, the second region having a second thermal conductivity different from the first thermal conductivity.
2. The layered photonic integrated circuit of claim 1 , wherein the first and second regions are separated by a gap.
3. The layered photonic integrated circuit of claim 1 , wherein the first region extends laterally beyond opposing lateral edges of the first waveguide.
4. The layered photonic integrated circuit of claim 1 , wherein the silicon layer optically isolates the first waveguide from the first region.
5. The layered photonic integrated circuit of claim 1 , wherein the second region extends laterally beyond opposing lateral edges of the second waveguide.
6. The layered photonic integrated circuit of claim 1 , wherein the second region is a diamond layer.
7. The layered photonic integrated circuit of claim 1 , wherein the silicon layer optically isolates the second waveguide from the second region.
8. The layered photonic integrated circuit of claim 1 , wherein the second region is thicker than the first region.
9. The layered photonic integrated circuit of claim 1 , wherein the first waveguide comprises a passive optical device.
10. The layered photonic integrated circuit of claim 1 , wherein the second waveguide comprises an active optical device.
11. The layered photonic integrated circuit of claim 1 , wherein:
the first and second thermal conductivities represent respective rates of heat transfer in the first and second regions; and
a rate of heat transfer in the first region is different from a rate of heat transfer in the second region.
12. A layered photonic integrated circuit comprising:
a silicon layer having a top side that defines a plane extending in a lateral direction;
a first waveguide positioned on the top side of the silicon layer;
a first region positioned on a bottom side of the silicon layer and laterally aligned with the first waveguide, the first region having a first thermal conductivity;
a second waveguide positioned on the top side of the silicon layer and laterally offset from the first waveguide;
a second region positioned on the bottom side of the silicon layer and laterally aligned with the second waveguide, the second region having a second thermal conductivity different from the first thermal conductivity; and
a silicon substrate positioned on a bottom side of the first region and a bottom side of the second region.
13. The layered photonic integrated circuit of claim 12 , wherein the first and second regions are separated by a gap that extends through the silicon substrate to the silicon layer.
14. The layered photonic integrated circuit of claim 12 , wherein the silicon layer optically isolates the first waveguide from the first region, and the silicon layer optically isolates the second waveguide from the second region.
15. A layered photonic integrated circuit, comprising:
a silicon layer having a top side that defines a plane extending in a lateral direction;
a passive optical device positioned on the top side of the silicon layer;
a buried oxide layer positioned on a bottom side of the silicon layer and laterally aligned with the passive optical device, the buried oxide layer having a first thermal conductivity;
an active optical device positioned on the top side of the silicon layer and laterally offset from the passive optical device; and
a diamond layer positioned on the bottom side of the silicon layer and laterally aligned with the active optical device, the diamond layer having a second thermal conductivity greater than the first thermal conductivity.
16. The layered photonic integrated circuit of claim 15 , wherein the buried oxide layer and the diamond layer are separated by a gap.
17. The layered photonic integrated circuit of claim 15 , further comprising a silicon substrate positioned on a bottom side of the buried oxide layer and a bottom side of the diamond layer, wherein the buried oxide layer and the diamond layer are separated by a gap that extends through the silicon substrate to the silicon layer.
18. The layered photonic integrated circuit of claim 15 , wherein:
the buried oxide layer extends laterally beyond opposing lateral edges of the passive optical device; and
the diamond layer extends laterally beyond opposing lateral edges of the active optical device.
19. The layered photonic integrated circuit of claim 15 , wherein the diamond layer is thicker than the buried oxide layer.
20. A method of manufacturing a layered photonic integrated circuit, the method comprising:
forming a silicon layer having a top side that defines a plane extending in a lateral direction;
forming a first waveguide positioned on the top side of the silicon layer;
forming a first region positioned on a bottom side of the silicon layer and laterally aligned with the first waveguide, the first region having a first thermal conductivity, the first region being a buried oxide layer;
forming a second waveguide positioned on the top side of the silicon layer and laterally offset from the first waveguide; and
forming a second region positioned on the bottom side of the silicon layer and laterally aligned with the second waveguide, the second region having a second thermal conductivity different from the first thermal conductivity.