USB controller with automatic clock generation and method thereof

1. A USB controller with automatic clock generation, comprising:

an oscillator, for generating an initial clock;

a first phase locked loop (PLL), used for receiving the initial clock and outputting a controller operating clock having a first frequency;

a controller, used for detecting at least one universal serial bus device and outputting an initial frame signal having a second frequency;

a second phase lock loop (PLL), used for receiving the initial frame signal and outputting a sync frame signal having the first frequency;

a third phase lock loop (PLL), for receiving the sync frame signal and outputting a stabilizing frame signal having the first frequency; and

a multiplexer, used for receiving the controller operating clock and the stabilizing frame signal and transmitting the controller operating clock or the stabilizing frame signals to the controller;

wherein the controller operating clock being obtained with frequency multiplication of the initial clock by the first PLL; the sync frame signal being obtained with frequency multiplication of the initial frame signal by the second PLL; and the stabilizing frame signal being obtained with jitter and noise filtering of the sync frame signal by the third PLL to make the stabilizing frame signal conforming to USB transmission specification;

wherein the second PLL comprising: a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frame signal detector; the LPF of the second PLL having a default value; when the frame signal detector detecting a first initial frame signal (SOF), the frame signal detector automatically calculating the required default value for the VCO corresponding to the second PLL and the third PLL to have a complete initial frame signal (SOF), initializing the second PLL and the third PLL, and activating the second PLL and the third PLL when a third initial frame signal (SOF) appearing.

2. The USB controller with automatic clock generation as claimed in claim 1 , wherein the initial clock is at 12 MHz.

3. The USB controller with automatic clock generation as claimed in claim 1 , wherein the controller operating clock is between 48 MHz and 5 GHz.

4. The USB controller with automatic clock generation as claimed in claim 1 , wherein the first PLL and the third PLL comprise respectively: a phase detector, a low-pass filter, a voltage-controlled oscillator, a first frequency divider, and a second frequency divider.

5. The USB controller with automatic clock generation as claimed in claim 1 , wherein the second PLL further comprises: a phase detector, and a frequency divider.

6. A method of USB controller with automatic clock generation, comprising the steps of:

Step 1: using an oscillator to generate an initial clock; Step 2: using a first phase locked loop (PLL) for receiving the initial clock and outputting a controller operating clock having a first frequency; Step 3: using a multiplexer for receiving the controller operating clock and transmitting the controller operating clock to a controller; Step 4: using the controller for detecting at least one universal serial bus device and outputting an initial frame signal having a second frequency; Step 5: using a second phase lock loop (PLL) for receiving the initial frame signal and outputting a sync frame signal having the first frequency; Step 6: using a third phase lock loop (PLL) for receiving the sync frame signal and outputting a stabilizing frame signal having the first frequency; Step 7: using the multiplexer for receiving the stabilizing frame signal and transmitting the stabilizing frame signals to the controller; wherein the controller operating clock being obtained with frequency multiplication of the initial clock by the first PLL; the sync frame signal being obtained with frequency multiplication of the initial frame signal by the second PLL; and the stabilizing frame signal being obtained with jitter and noise filtering of the sync frame signal by the third PLL to make the stabilizing frame signal conforming to USB transmission specification; wherein the second PLL comprising: a low-pass filter (LPF), a voltage-controlled oscillator (VCO), and a frame signal detector; the LPF of the second PLL having a default value; when the frame signal detector detecting a first initial frame signal (SOF), the frame signal detector automatically calculating the required default value for the VCO corresponding to the second PLL and the third PLL to have a complete initial frame signal (SOF), initializing the second PLL and the third PLL, and activating the second PLL and the third PLL when a third initial frame signal (SOF) appearing.

7. The method of USB controller with automatic clock generation as claimed in claim 6 , wherein the initial clock is at 12 MHz.

8. The method of USB controller with automatic clock generation as claimed in claim 6 , wherein the controller operating clock is between 48 MHz and 5 GHz.

9. The method of USB controller with automatic clock generation as claimed in claim 6 , wherein the first PLL and the third PLL comprise respectively: a phase detector, a low-pass filter, a voltage-controlled oscillator, a first frequency divider, and a second frequency divider.

10. The method of USB controller with automatic clock generation as claimed in claim 6 , wherein the second PLL further comprises: a phase detector, and a frequency divider.