Efficient digital duty cycle adjusters
The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.
1. An apparatus of an efficient digital duty cycle adjuster comprising:
an input clock having an input clock duty cycle;
at least one programmable delay line inserting a programmable delay to the input clock, wherein the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, and wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and
a selecting circuit generating an output clock having an output clock duty cycle, wherein the selecting circuit includes a select signal, the select signal is determined in accordance with the first delay and the second delay, the output clock duty cycle is adjusted by the programmable delay, and the output clock has a rise edge aligned with a rise edge of the delayed rise edge and a fall edge aligned with a fall edge of the delayed fall edge.
2. The apparatus of claim 1 , wherein the programmable delay is configured in accordance with a duty cycle correct range and a clock period of the input clock.
3. The apparatus of claim 1 , wherein the second delay includes the programmable delay and an intrinsic delay, and the first delay includes a match cell delay, and the match cell delay equals the intrinsic delay.
4. The apparatus of claim 1 , further comprising a static mux having a static select signal, wherein the static select signal is determined by the input clock duty cycle.
5. The apparatus of claim 4 , wherein the static mux includes two inputs, and one input is inverted of the other input.
6. The apparatus of claim 1 , wherein the selecting circuit includes edge trigged flip flops trigged at opposite edges, the edge trigged flip flops include a positive flip flop trigged at positive edge and a negative flip flop triggered at negative edge, the delayed rise edge is connected to the clock of the positive flip flop, and the delayed fall edge is connected to the clock of the negative flip flop.
7. The apparatus of claim 6 , wherein the selecting circuit includes an AND gate, the outputs of the positive flip flop and the negative flip flop are connected to the inputs of the AND gate, and the output of the AND gate is used to reset the positive flip flop and the negative flip flop.
8. The apparatus of claim 7 , further comprising a fixed delay Tb inserted before the reset pin of the negative flip flop.
9. The apparatus of claim 8 , wherein the selecting circuit includes an inverted AND gate with an inverted input, the output of the negative flip flop is connected to the inverted input of the inverted AND gate, and the output of the positive flip flop is connected to the other input of the inverted AND gate.
10. The apparatus of claim 8 , further comprising a power-up sequencer, wherein the power-up sequencer includes a synchronizer and an OR gate, the output of the synchronizer and the output of the AND gate are connected to the inputs of the OR gate, and the output of the OR gate is used to reset the positive flip flop and the negative flip flop.
11. The apparatus of claim 10 , wherein the synchronizer comprises at least 2 sequentially connected negative-triggered flip flops, a power down signal is connected to the input of the synchronizer and the set pins of the negative-triggered flip flops, and the delayed fall edge is connected to the clock pins of the negative-triggered flip flops.
12. The apparatus of claim 6 , wherein the selecting circuit includes an XOR gate, and the outputs of the positive flip flop and the negative flip flop are connected to inputs of the XOR gate.
13. The apparatus of claim 1 , wherein the selecting circuit includes an OR gate, the delayed first edge and the delay second edge are connected to inputs of the OR gate.
14. The apparatus of claim 1 , wherein the output clock duty cycle is different than the input clock duty cycle.
15. An apparatus of an efficient duty cycle adjuster, comprising:
an input clock having an input clock duty cycle;
at least one programmable delay line inserting a programmable delay to the input clock, wherein the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, and wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and
a selecting circuit generating an output clock having an output clock duty cycle, wherein the selecting circuit includes a select signal, the select signal is determined in accordance with the first delay and the second delay, the output clock duty cycle is adjusted by the programmable delay;
wherein the selecting circuit includes a dynamic mux, and a fixed delay element is inserted before the select signal.
16. A method of operation of an efficient digital duty cycle adjuster comprising:
providing an input clock having an input clock duty cycle;
inserting at least one programmable delay of a programmable delay line to the input clock, wherein the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, and wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and
adjusting an output clock duty cycle of an output clock by configuring the programmable delay, including aligning a rise edge of the output clock with a rise edge of the delayed rise edge and aligning a fall edge of the output clock with a fall edge of the delayed fall edge, wherein the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.
17. The method of claim 16 , wherein the inserting the programmable delay includes configuring the programmable delay in accordance with a duty cycle correct range and a clock period of the input clock.
18. The method of claim 16 , wherein the inserting the programmable delay of the programmable delay line includes inserting the programmable delay and an intrinsic delay for the second delay, a match cell delay for the first delay, and the match cell delay equals the intrinsic delay.