Vertical gate-all-around TFET
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.
1. A method, comprising:
forming a doped well in the substrate;
forming a pillar from a top surface of the doped well, the forming of the pillar including:
forming a drain region;
forming a channel region on the drain region; and
forming a source region on the channel region;
forming a gate structure surrounding the channel region; and
forming a back side contact to the drain region, the back side contact being separated from the pillar by the doped well.
2. The method of claim 1 , further comprising:
forming a front side contact on the source region.
3. The method of claim 2 , further comprising:
forming a spacer around the pillar between the gate structure and the front side contact.
4. The method of claim 2 , further comprising:
forming a spacer around the pillar between the gate structure and the doped well.
5. The method of claim 2 wherein the front side contact has a first portion and a second portion, the first portion being on the second portion, the second portion encapsulating a first end of the pillar, the first portion having a greater width than the second portion.
6. The method of claim 5 wherein the first portion encapsulates a middle portion of the pillar.
7. The method of claim 1 , further comprising:
forming a mask on the substrate, the mask having an opening, the pillar extending through the opening.
8. The method of claim 1 wherein the gate structure is a gate-all-around structure that encapsulates a portion of the channel region.
9. A method, comprising:
forming a well in a substrate, the substrate having a first surface and a second surface opposite the first surface, the well extending from the first surface to the second surface, the substrate having a first portion and a second portion, each portion extending from the first surface to the second surface, the well positioned between the first portion and the second portion, each of the first and second portions having a different doping concentration than the well;
forming a nanowire extending from the well from the first surface;
forming a first contact on a first end of the nanowire; and
forming a second contact adjacent to a second end of the nanowire, the second end of the nanowire being adjacent to the well.
10. The method of claim 9 wherein the forming the second contact includes forming the second contact on the second surface at the well.
11. The method of claim 9 wherein the nanowire has a polarity opposite that of the well.
12. The method of claim 9 wherein the forming the first contact includes:
forming a first portion having a first width adjacent to the first end of the nanowire; and
forming a second portion on the first portion, the second portion having a second width, the second width greater than the first width.
13. The method of claim 12 wherein the forming the first contact includes forming a T-shaped contact.
14. The method of claim 9 wherein the forming the first contact includes forming a portion of the first contact on a middle portion of the nanowire, the middle portion of the nanowire between the first end and the second end.
15. The method of claim 9 , further comprising:
forming a second well in the substrate, the second well extending from the first surface to the second surface, the substrate having a third portion extending from the first surface to the second surface, the second well positioned between the second portion and the third portion;
forming a second nanowire extending from the second well from the first surface;
forming a third contact on a first end of the second nanowire; and
forming a fourth contact adjacent to a second end of the second nanowire, the second end of the second nanowire being adjacent to the second well.
16. The method of claim 9 , further comprising:
forming a conductive liner on the first end of the nanowire, the forming the first contact including forming the first contact on the conductive liner.
17. A method, comprising:
forming a doped region in a substrate, the substrate having a first surface and a second surface opposite the first surface, the doped region extending from the first surface to the second surface;
forming a nanowire on the substrate, the nanowire having a first end and a second end, the first end adjacent to the first surface of the substrate at the doped region;
forming a first electrical contact on the second end of the nanowire, the first electrical contact having a first dimension in a first direction; and
forming a second electrical contact on the second surface of the substrate at the doped region, the second electrical contact having a second dimension in the first direction, the second dimension greater than the first dimension.
18. The method of claim 17 , further comprising:
forming a gate around a middle portion of the nanowire.
19. The method of claim 17 wherein forming the nanowire includes forming a doped region in the second end of the nanowire.
20. The method of claim 17 wherein the forming a first electrical contact includes:
forming a contact body adjacent to the second end of the nanowire; and
forming a contact extension coupled to the contact body and surrounding the second end of the nanowire.