IP Library › Granted Patent US 10,223,122
Granted Patent B2
US 10,223,122 · App. 15/482,779 · Granted Mar 5, 2019

Managing event count reports in a tile-based architecture

Inventors: Ziyad S. Hakura (Gilroy, CA); Jerome F. Duluk, Jr. (Palo Alto, CA)
Assignee: NVIDIA CORPORATION
G06F9/38G06F9/44G06F12/0808G06F12/0875G06T1/20G06T1/60G06T15/005G06T15/405G06T15/503G06T15/80G06T17/20G09G5/003G09G5/395G06F2212/302Y02D10/13
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Quick Facts
Patent No.
US 10,223,122
App. No.
15/482,779
Granted
Mar 5, 2019
Kind
B2
Abstract

One embodiment of the present invention sets forth a graphics processing system configured to track event counts in a tile-based architecture. The graphics processing system includes a screen-space pipeline and a tiling unit. The screen-space pipeline includes a first unit, a count memory associated with the first unit, and an accumulating memory associated with the first unit. The first unit is configured to detect an event type and increment the count memory. The tiling unit is configured to cause the screen-space pipeline to update an external memory address to reflect a first value stored in the count memory when the first unit completes processing of a first set of primitives. The tiling unit is also configured to cause the screen-space pipeline to update the accumulating memory to reflect a second value stored in the count memory when the first unit completes processing of a second set of primitives.

Claims (30)

1. A graphics processing system, comprising:

a screen-space pipeline that includes a count memory and an accumulating memory; and

a tiling unit that causes the screen-space pipeline to increment a value stored at an external memory address by a first value stored in the count memory when a first unit has completed processing a first set of primitives that overlap a first cache tile, and causes the screen-space pipeline to update the accumulating memory to reflect a second value stored in the count memory when the first unit has completed processing a second set of primitives that overlap the first cache tile.

2. The graphics processing system of claim 1 , wherein the tiling unit receives a first plurality of primitives that includes the first set of primitives, receives a second plurality of primitives that includes the second set of primitives, determines that the first set of primitives overlaps the first cache tile, and determines that the second set of primitives overlaps the first cache tile.

3. The graphics processing system of claim 1 , wherein the tiling unit receives a report request for a final count value associated with a first plurality of primitives that includes the first set of primitives.

4. The graphics processing system of claim 1 , wherein the tiling unit transmits the first set of primitives, the second set of primitives, and a first set of commands to the screen-space pipeline for processing, wherein the first set of commands includes a first command that causes the screen-space pipeline to increment the value stored at the external memory address after processing the first command.

5. The graphics processing system of claim 4 , wherein the first set of commands further includes a second command that causes the accumulating memory to store the second value stored in the count memory when the first unit has completed processing the second set of primitives.

6. The graphics processing system of claim 5 , wherein the first set of commands further includes a third command that causes the count memory to be reset after the second command is processed.

7. The graphics processing system of claim 4 , wherein the first set of commands further includes a second command that causes the second value to be added to the accumulating memory when the first unit has completed processing the second set of primitives.

8. The graphics processing system of claim 7 , wherein the first set of commands further includes a third command that causes the count memory to be reset after the second command is processed.

9. The graphics processing system of claim 4 , wherein the first set of commands further includes a second command that causes the second value to be added to the accumulating memory when the first unit has completed processing the second set of primitives, and the first set of commands further includes a third command that causes the count memory to store a value equal to a value stored in the accumulating memory after the second command is processed.

10. The graphics processing system of claim 1 , wherein at least one primitive in the first set of primitives and at least one primitive in the second set of primitives cause the first unit to detect the event type and increment the count memory.

11. A computing device, comprising:

a memory; and

a graphics processing system that is coupled to the memory and includes:

a screen-space pipeline having a count memory and an accumulating memory; and

a tiling unit that causes the screen-space pipeline to increment a value stored at an external memory address by a first value stored in the count memory when a first unit has completed processing a first set of primitives, and causes the screen-space pipeline to update the accumulating memory to reflect a second value stored in the count memory when the first unit has completed processing a second set of primitives.

12. The computing device of claim 11 , wherein the tiling unit receives a first plurality of primitives that includes the first set of primitives, receives a second plurality of primitives that includes the second set of primitives, determines that the first set of primitives overlaps a first cache tile, and determines that the second set of primitives overlaps the first cache tile.

13. The computing device of claim 11 , wherein the tiling unit receives a report request for a final count value associated with a first plurality of primitives that includes the first set of primitives.

14. The computing device of claim 11 , wherein the tiling unit transmits the first set of primitives, the second set of primitives, and a first set of commands to the screen-space pipeline for processing, wherein the first set of commands includes a first command that causes the screen-space pipeline to increment the value stored at the external memory address after processing the first command.

15. The computing device of claim 14 , wherein the first set of commands further includes a second command that causes the accumulating memory to store the second value stored in the count memory when the first unit has completed processing the second set of primitives.

16. The computing device of claim 15 , wherein the first set of commands further includes a third command that causes the count memory to be reset after the second command is processed.

17. The computing device of claim 14 , wherein the first set of commands further includes a second command that causes the second value to be added to the accumulating memory when the first unit has completed processing the second set of primitives.

18. The computing device of claim 17 , wherein the first set of commands further includes a third command that causes the count memory to be reset after the second command is processed.

19. The computing device of claim 14 , wherein the first set of commands further includes a second command that causes the second value to be added to the accumulating memory when the first unit has completed processing the second set of primitives, and the first set of commands further includes a third command that causes the count memory to store a value equal to a value stored in the accumulating memory after the second command is processed.

20. The computing device of claim 11 , wherein at least one primitive in the first set of primitives and at least one primitive in the second set of primitives cause the first unit to detect the event type and increment the count memory.

21. The computer-implemented method of claim 20 , wherein at least one primitive in the first set of primitives and at least one primitive in a second set of primitives cause the first unit to detect the event type and increment the count memory.

22. The computer-implemented method of claim 20 , further comprising receiving a first plurality of primitives that includes the primitives in the first set of primitives, receiving a second plurality of primitives that includes primitives in a second set of primitives, determining that the first set of primitives overlaps the first cache tile, and determining that the second set of primitives overlaps the first cache tile.

23. A computer-implemented method, comprising:

causing a screen-space pipeline to increment a value stored at an external memory address by a first value stored in a count memory when a first unit included in the screen-space pipeline and associated with the count memory has completed processing a first set of primitives that overlap a first cache tile.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2017
From: HAKURA, ZIYAD S.; DULUK, JEROME F., JR.
To: NVIDIA CORPORATION
Reel/Frame 041935/0172 →
Continuity (3)
Continuation 14046249 · Oct 4, 2013
Provisional Application 61719271 · Oct 26, 2012
Related Publication 20170213313A1 · Jul 27, 2017