Schottky-CMOS asynchronous logic cells

1. An integrated circuit implementing a NAND gate system, the integrated circuit comprising:

a first input coupled to a cathode of a first p-type Schottky diode;

x additional inputs coupled to x respective cathodes of x additional p-type Schottky diodes;

a first n-type transistor including a gate node that is coupled to an anode of the first Schottky diode and x respective anodes of the x additional Schottky diodes; and

a p-type transistor including a gate node that is coupled to the anode of the first Schottky diode and x respective anodes of the x additional Schottky diodes;

a second n-type transistor including a gate node that is coupled to the cathode of the first p-type Schottky diode; and

x additional n-type transistors including x respective gate nodes that are coupled to the x respective cathodes of the x additional p-type Schottky diodes;

wherein an output is coupled to a non-gate node of the first n-type transistor and a non-gate node of the p-type transistor.

2. The integrated circuit of claim 1 , wherein a threshold forward voltage of the first p-type Schottky diode is less than a threshold voltage of the second n-type transistor.

3. The integrated circuit of claim 1 , wherein:

a threshold forward voltage of a respective p-type Schottky diode of the x additional p-type Schottky diodes is less than a threshold forward voltage of a respective n-type transistor of the x additional n-type transistors, and

a respective additional input of the x additional inputs is coupled to the respective p-type Schottky diode and the respective n-type transistor.

4. The integrated circuit of claim 1 , wherein a threshold forward voltage of the first p-type Schottky diode is less than a threshold voltage of the first n-type transistor.

5. The integrated circuit of claim 1 , wherein a threshold forward voltage of the first p-type Schottky diode is less than a threshold voltage of the p-type transistor.

6. The integrated circuit of claim 1 , wherein the integrated circuit is configured for asynchronous operation.

7. The integrated circuit of claim 1 , wherein the x additional n-type transistors include a second n-type transistor that is connected in series with a third n-type transistor.

8. The integrated circuit of claim 1 , wherein x is greater than or equal to four.

9. The integrated circuit of claim 8 , wherein a propagation delay of the integrated circuit is less than 80 picoseconds.

10. The integrated circuit of claim 8 , wherein a layout area required for the integrated circuit is less than 2.0 μm 2 .

11. The integrated circuit of claim 8 , wherein the root mean square (RMS) power required for the integrated circuit is less than 50 microwatts.

12. An integrated circuit implementing a NOR gate system, the integrated circuit comprising:

a first input coupled to an anode of a first n-type Schottky diode;

x additional inputs coupled to x respective anodes of x additional n-type Schottky diodes;

a first p-type transistor including a gate node that is coupled to a cathode of the first n-type Schottky diode and a cathode of the x additional n-type Schottky diodes; and

an n-type transistor including a gate node that is coupled to the cathode of the first n-type Schottky diode and the cathodes of the x additional n-type Schottky diodes;

a second p-type transistor including a gate node that is coupled to the anode of the first n-type Schottky diode; and

x additional p-type transistors including x respective gate nodes that are coupled to the x respective anodes of the x additional n-type Schottky diodes;

wherein an output is coupled to a non-gate node of the first p-type transistor and a non-gate node of the n-type transistor.

13. The integrated circuit of claim 12 , wherein a threshold forward voltage of the first n-type Schottky diode is less than a threshold voltage of the second p-type transistor.

14. The integrated circuit of claim 12 , wherein:

a threshold forward voltage of a respective n-type Schottky diode of the x additional n-type Schottky diodes is less than a threshold forward voltage of a respective p-type transistor of the x additional p-type transistors, and

a respective additional input of the x additional inputs is coupled to the respective n-type Schottky diode and the respective p-type transistor.

15. The integrated circuit of claim 12 , wherein the integrated circuit is configured for asynchronous operation.

16. The integrated circuit of claim 12 , wherein the x additional p-type transistors include a second p-type transistor that is connected in series with a third p-type transistor.

17. An integrated circuit implementing an x-input logic gate, the integrated circuit comprising:

a plurality of Schottky diodes that includes x Schottky diodes; and

a plurality of source-follower transistors that includes x source-follower transistors, wherein:

each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode; and

a first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

18. The integrated circuit of claim 17 , wherein:

a threshold forward voltage of a respective Schottky diode of the x Schottky diodes is less than a threshold forward voltage of a respective source-follower transistor of the x source-follower transistors, and

an input of the integrated circuit is coupled to the respective Schottky diode and the respective source-follower transistor.

19. The integrated circuit of claim 17 , wherein the integrated circuit is configured for asynchronous operation.