IP Library › Granted Patent US 10,840,174
Granted Patent B2
US 10,840,174 · App. 15/485,681 · Granted Nov 17, 2020

Metallic synapses for neuromorphic and evolvable hardware

Inventors: Shawn P. Fetterolf (Cornwall, VT); Jin-Ping Han (Yorktown Heights, NY); Christian Lavoie (Pleasantville, NY); Paul S. McLaughlin (Poughkeepsie, NY); Ahmet S. Ozcan (San Jose, CA); Roger A. Quon (Rhinebeck, NY)
Assignee: Samsung Electronics Co., Ltd.
H01L23/49827G06N3/0635G06N3/084G06N3/049G06N3/082G06N3/126
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Quick Facts
Patent No.
US 10,840,174
App. No.
15/485,681
Granted
Nov 17, 2020
Kind
B2
Abstract

Technical solutions are described for configuring a synaptic array. An example computer implemented method includes selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task. The method further includes connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by forming a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit.

Claims (28)

1. A computer implemented method for configuring a synaptic array, the method comprising:

selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task; and

connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by applying a predetermined voltage to the first connector that forms a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit, wherein the metallic protrusion is formed at a predetermined portion of the first connector, and wherein the predetermined portion is deposited with an implant material that reduces an extrusion voltage threshold of the predetermined portion to a value below the predetermined voltage that is applied.

2. The computer implemented method of claim 1 , wherein the first electronic circuit is a memory unit.

3. The computer implemented method of claim 1 , wherein the first electronic circuit is a processing unit.

4. The computer implemented method of claim 1 , wherein the particular portion of the first connector has a barrier of a first thickness that is lesser than a second thickness of the barrier on other portions of the first connector.

5. The computer implemented method of claim 1 , wherein the first connector and the second connector are parallel to each other.

6. The computer implemented method of claim 1 , wherein the first connector and the second connector are oriented at a predetermined angle to each other.

7. A neuromorphic system comprising:

a synaptic array; and

a neuromorphic controller coupled with the synaptic array for configuring the synaptic array by:

selecting a first electronic circuit and a second electronic circuit from the synaptic array for executing a task; and

connecting the first electronic circuit to the second electronic circuit to facilitate passage of electric current by applying a predetermined voltage to the first connector that forms a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit, wherein the metallic protrusion is formed at a predetermined portion of the first connector, and wherein the predetermined portion is deposited with an implant material that reduces an extrusion voltage threshold of the predetermined portion to a value below the predetermined voltage that is applied.

8. The neuromorphic system of claim 7 , wherein the first electronic circuit is a memory unit.

9. The neuromorphic system of claim 7 , wherein the first connector and the second connector are within a predetermined distance from each other.

10. The neuromorphic system of claim 7 , wherein the first connector and the second connector are parallel to each other.

11. The neuromorphic system of claim 7 , wherein the first connector and the second connector are oriented at a predetermined angle to each other.

12. The neuromorphic system of claim 7 , wherein the first electronic circuit is a processing unit.

13. The neuromorphic system of claim 7 , wherein the predetermined portion of the first connector has a barrier of a first thickness that is lesser than a second thickness of remaining portions of the first connector.

14. A computer program product for configuring a synaptic array, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by a processing circuit to cause the processing circuit to:

select a first electronic circuit and a second electronic circuit from the synaptic array for executing a task; and

connect the first electronic circuit to the second electronic circuit to facilitate passage of electric current by applying a predetermined voltage to the first connector that forms a metallic protrusion to connect a first connector of the first electronic circuit and a second connector of the second electronic circuit, wherein the metallic protrusion is formed at a predetermined portion of the first connector, and wherein the predetermined portion is deposited with an implant material that reduces an extrusion voltage threshold of the predetermined portion to a value below the predetermined voltage that is applied.

15. The computer program product of claim 14 , wherein the first electronic circuit is a memory unit.

16. The computer program product of claim 14 , wherein the first electronic circuit is a processing unit.

17. The computer program product of claim 14 , wherein the first connector and the second connector are within a predetermined distance from each other.

18. The computer program product of claim 14 , wherein the first connector and the second connector are parallel to each other.

19. The computer program product of claim 14 , wherein the first connector and the second connector are oriented at a predetermined angle to each other.

20. The computer program product of claim 14 , wherein the predetermined portion of the first connector has a barrier of a first thickness that is lesser than a second thickness of remaining portions of the first connector.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 053276/0136 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2017
From: FETTEROLF, SHAWN P.; HAN, JIN-PING; LAVOIE, CHRISTIAN; MCLAUGHLIN, PAUL S.; OZCAN, AHMET S.; QUON, ROGER A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041984/0885 →
Continuity (1)
Related Publication 20180300599A1 · Oct 18, 2018