System and method for arbitration and recovery of SPD interfaces in an information handling system

1. An information handling system, comprising:

a Dual In-Line Memory Module (DIMM) including a Serial Presence Detect (SPD) and a slave Inter-Integrated Circuit (I2C) interface configured to provide communicative access to the SPD;

a processor complex including a first master I2C interface selectively coupled to the slave I2C interface, the processor complex configured to communicate with the SPD during a system boot state;

a Baseboard Management Controller (BMC) including a second master I2C interface selectively coupled to the slave I2C interface, the BMC configured to communicate with the SPD during a power-off state of the information handling system; and

reset logic configured to:

select the first master I2C interface to be coupled to the slave I2C interface during the system boot state;

select the second master I2C interface to be coupled to the slave I2C interface during the power-off state;

detect a transition between the power-off state and the system boot state; and

delay the selection of the first master I2C interface to be coupled to the slave I2C interface until the BMC is finished communicating with the SPD.

2. The information handling system of claim 1 , further comprising:

a multiplexor configured to selectively couple the first master I2C interface to the slave I2C interface.

3. The information handling system of claim 2 , further comprising:

a switch configured to selectively couple the second master I2C interface to the slave I2C interface.

4. The information handling system of claim 3 , wherein the reset logic includes an enable signal, wherein the enable signal operates to select the first master I2C interface to be coupled to the slave I2C interface when the enable signal is in a first state and to select the second master I2C interface select to be coupled to the slave I2C interface when the enable signal is in a second state.

5. The information handling system of claim 4 , wherein the reset logic is further configured to: provide the enable signal in the first state during the system boot state; and provide the enable signal in the second state during the power-off state.

6. The information handling system of claim 1 , wherein the reset logic is further configured to:

set a SPD-bus-healthy bit in a Serial Peripheral Interface (SPI) in response to detecting the transition between the power-off state and the system boot state.

7. The information handling system of claim 6 , wherein the BMC is configured to:

detect that the SPD-bus-health bit is set;

perform a I2C bus status check in response to detecting that the SPD-bus-healthy bit is set; and

clear the SPD-bus-healthy bit in response to the I2C bus status check.

8. The information handling system of claim 7 , wherein the reset logic is further configured to: determine that the SPD-bus-healthy bit is cleared.

9. The information handling system of claim 8 , wherein the reset logic determines that the BMC is finished communicating with the SPD based upon the determination that the SPD-bus-healthy bit is cleared.

10. A method, comprising:

selecting, by reset logic of an information handling system, a first master Inter-Integrated Circuit (I2C) interface of a processor complex of the information handling system, to be coupled to a slave I2C interface of a Dual In-Line Memory Module (DIMM) of the information handling system during a system boot state of the information handling system, wherein the slave I2C interface is configure to provide communicative access to a Serial Presence Detect (SPD) of the DIMM;

selecting, by the reset logic, a second master I2C interface of a Baseboard Management Controller (BMC) of the information handling system, to be coupled to the slave I2C interface during a power-off state of the information handling system;

detecting, by the reset logic, a transition between the power-off state and the system boot state; and

delaying, by the reset logic, the selection of the first master I2C interface to be coupled to the slave I2C interface until the BMC is finished communicating with the SPD.

11. The method of claim 10 , wherein, in selecting the first master I2C interface to be couple to the slave I2C interface, the method further comprises:

enabling, by the reset logic, a multiplexor configured to selectively couple the first master I2C interface to the slave I2C interface.

12. The method of claim 11 , wherein, in selecting the second master I2C interface to be couple to the slave I2C interface, the method further comprises:

enabling, by the reset logic, a switch configured to selectively couple the second master I2C interface to the slave I2C interface.

13. The method of claim 12 , wherein the reset logic includes an enable signal, wherein:

in enabling the multiplexor, the method further comprises providing, by the reset logic, the enable signal in a first state; and

in enabling the switch, the method further comprises providing, by the reset logic, the enable signal in a second state.

14. The method of claim 13 , further comprising:

providing, by the reset logic, the enable signal output in the first state during the system boot process; and

providing, by the reset logic, the enable signal output in the second state during the power-off state.

15. The method of claim 10 , further comprising:

setting, by the reset logic, a SPD-bus-healthy bit in a Serial Peripheral Interface (SPI) in response to detecting the transition between the power-off state and the system boot state.

16. The method of claim 15 , further comprising:

detecting, by the BMC, that the SPD-bus-health bit is set;

performing, by the BMC, a I2C bus status check in response to detecting that the SPD-bus-healthy bit is set; and

clearing, by the BMC, the SPD-bus-healthy bit in response to the I2C bus status check.

17. The method of claim 16 , further comprising: determining, by the reset logic, that the SPD-bus-healthy bit is cleared.

18. The method of claim 17 , wherein the reset logic determines that the BMC is finished communicating with the SPD based upon the determination that the SPD-bus-healthy bit is cleared.

19. Reset logic circuitry of an information handling system, comprising:

an enable signal output; and

reset logic hardware configured to:

set the enable signal output to a first state to select a first master Inter-Integrated Circuit (I2C) interface of a processor complex of the information handling system, to be coupled to a slave I2C interface of a Dual In-Line Memory Module (DIMM) of the information handling system during a system boot state of the information handling system, wherein the slave I2C interface is configure to provide communicative access to a Serial Presence Detect (SPD) of the DIMM;

set the enable signal output to a second state to select a second master I2C interface of a Baseboard Management Controller (BMC) of the information handling system, to be coupled to the slave I2C interface during a power-off state of the information handling system;

detect a transition between the power-off state and the system boot state; and

delay the selection of the first master I2C interface to be coupled to the slave I2C interface until the BMC is finished communicating with the SPD.

20. The reset logic circuitry of claim 19 , wherein the reset logic hardware is further configured to: set a SPD-bus-healthy bit in a Serial Peripheral Interface (SPI) in response to detecting the transition between the power-off state and the system boot state; and determine that the SPD-bus-healthy bit is cleared, wherein the reset logic hardware determines that the BMC is finished communicating with the SPD based upon the determination that the SPD-bus-healthy bit is cleared.