Programmable logic devices with multi-level input/output signals
View Patent ↗One aspect provides a programmable logic device. The device includes an input circuit for detecting a multi-level input signal and an output circuit. The input circuit includes: an input pin for receiving the multi-level input signal; first and second programmable voltage generators to generate, respectively, first and second multi-level voltage signals; a pair of comparators, each comparator having a first input coupled to the input pin and a second input coupled to a corresponding programmable voltage generator; and a logic gate coupled to the comparators, thereby facilitating the detection of the multi-level input signal based on outputs of the comparators. The output circuit includes a third programmable voltage generator to generate a third multi-level voltage signal, an output pin, and a voltage buffer coupling the third programmable voltage generator to the output pin, thereby facilitating the programmable logic device to output, over the output pin, the third multi-level voltage signal.
1 . A programmable logic device, comprising:
an input circuit for detecting a multi-level input signal, wherein the input circuit comprises:
an input pin for receiving the multi-level input signal;
first and second programmable voltage generators to generate, respectively, first and second multi-level voltage signals;
a pair of comparators, wherein each comparator has a first input coupled to the input pin and a second input coupled to a corresponding programmable voltage generator; and
a logic gate coupled to the comparators, thereby facilitating the detection of the multi-level input signal based on outputs of the comparators; and
an output circuit comprising:
a third programmable voltage generator to generate a third multi-level voltage signal;
an output pin; and
a voltage buffer coupling the third programmable voltage generator to the output pin, thereby facilitating the programmable logic device to output, over the output pin, the third multi-level voltage signal.
2 . The programmable logic device of claim 1 , wherein each programmable voltage generator comprises a control logic to output a binary bit sequence and a digital-to-analog converter (DAC) to convert the binary bit sequence to a corresponding multi-level voltage signal.
3 . The programmable logic device of claim 2 , wherein the control logic is to output a time-varying binary bit sequence.
4 . The programmable logic device of claim 2 , wherein the DAC comprises an R-2R resistor ladder network.
5 . The programmable logic device of claim 1 , wherein each comparator comprises a differential amplifier.
6 . The programmable logic device of claim 5 , wherein the first multi-level voltage signal is lower than the second multi-level voltage signal, wherein the first multi-level voltage signal is sent to a positive input of the differential amplifier of one comparator, and wherein the second multi-level voltage signal is sent to a negative input of the differential amplifier of the other comparator.
7 . The programmable logic device of claim 6 , wherein the logic gate is an AND gate.
8 . The programmable logic device of claim 7 , wherein the logic gate is to output a logic “1” in response to detecting that the multi-level input signal is in a range between the first and second multi-level voltage signals.
9 . The programmable logic device of claim 1 , wherein the voltage buffer comprises a unity gain operational amplifier.
10 . A circuit for detecting a multi-level input signal received at a programmable logic device, the circuit comprising:
an input pin for receiving the multi-level input signal;
first and second programmable voltage generators to generate, respectively, first and second multi-level voltage signals;
a pair of comparators, wherein each comparator has a first input coupled to the input pin and a second input coupled to a corresponding programmable voltage generator; and
a logic gate coupled to the comparators, thereby facilitating the detection of the multi-level input signal based on outputs of the comparators.
11 . The circuit of claim 10 , wherein each programmable voltage generator comprises a control logic to output a binary bit sequence and a digital-to-analog converter (DAC) to convert the binary bit sequence to a corresponding multi-level voltage signal.
12 . The circuit of claim 11 , wherein the control logic is to output a time-varying bit sequence.
13 . The circuit of claim 11 , wherein the DAC comprises an R-2R resistor ladder network.
14 . The circuit of claim 10 , wherein each comparator comprises a differential amplifier.
15 . The circuit of claim 14 , wherein the first multi-level voltage signal is lower than the second multi-level voltage signal, wherein the first multi-level voltage signal is sent to a positive input of the differential amplifier of one comparator, and wherein the second multi-level voltage signal is sent to a negative input of the differential amplifier of the other comparator.
16 . The circuit of claim 15 , wherein the logic gate is an AND gate.
17 . The circuit of claim 16 , wherein the logic gate is to output a logic “1” in response to detecting that the multi-level input signal is in a range between the first and second multi-level voltage signals.
18 . An output circuit of a programmable logic device, the circuit comprising:
a programmable voltage generator to generate a multi-level voltage signal;
an output pin; and
a voltage buffer coupling the programmable voltage generator to the output pin, thereby facilitating the programmable logic device to output, over the output pin, the multi-level voltage signal, wherein the programmable voltage generator comprises a control logic to output a binary bit sequence and a digital-to-analog converter (DAC) to convert the binary bit sequence to a corresponding multi-level voltage signal, and wherein the DAC comprises an R-2R resistor ladder network.
19 . The output circuit of claim 18 , wherein the voltage buffer comprises a unity gain operational amplifier.