Methods and apparatus for power management of a memory cell

1. An integrated circuit, comprising:

a voltage generator configured to generate a first voltage and a second voltage;

a voltage control circuit configured to generate a voltage control signal according to a predetermined parameter;

a data processing circuit, coupled to the voltage control circuit and the voltage generator, comprising a memory cell, wherein the memory cell is configured to operate:

in an active state and in an idle state according to a predetermined time cycle, the predetermined time cycle comprising a first time segment and a second time segment; and

according to a clock frequency, wherein the clock frequency is a multiple of the predetermined parameter;

a selector circuit, coupled between the voltage control circuit and the data processing circuit and responsive the voltage control signal, wherein:

the selector circuit is configured to selectively couple one of the first and the second voltage to the memory cell;

the voltage control circuit transmits the voltage control signal to the selector circuit according to the first time segment and the second time segment;

the first voltage is coupled to the memory cell substantially coincident with the active state; and

the second voltage is coupled to the memory cell substantially coincident with the idle state.

2. The integrated circuit according to claim 1 , wherein the predetermined time cycle is equal to an inverse of the predetermined parameter.

3. The integrated circuit according to claim 1 , wherein the first time segment is equal to an inverse of the clock frequency.

4. The integrated circuit according to claim 3 , wherein the second time segment is equal to a difference of the predetermined time cycle and the first time segment.

5. The integrated circuit according to claim 1 , wherein:

during the first time segment, the memory cell operates in the active state; and

during the second time segment, the memory cell operates in the idle state.

6. The integrated circuit according to claim 1 , wherein

when the memory cell operates in the active state, the memory cell is capable of reading and writing data; and

when the memory cell operates in the idle state, the memory cell is:

capable of retaining previously-written data; and

incapable of reading and writing new data.

7. The integrated circuit according to claim 1 , wherein:

the control circuit couples the first voltage to the memory cell during the first time segment; and

the control circuit couples the second voltage to the memory cell during the second time segment.

8. The integrated circuit according to claim 1 , wherein:

the predetermined parameter is a sampling frequency; and

the sampling frequency is selected according to a range of human hearing.

9. The integrated circuit according to claim 1 , wherein:

the first voltage is less than a maximum operating voltage of the memory cell and greater than a minimum operating voltage of the memory cell; and

the second voltage is less than the minimum operating voltage of the memory cell and greater than a minimum retention voltage of the memory cell.

10. A method for operating a system with a plurality of memory cells, comprising:

generating a clock signal with a clock frequency based on a sampling frequency;

generating a first voltage and a second voltage with a voltage generator;

simultaneously outputting, with the voltage generator, the first voltage at a first output terminal and the second voltage at a second output terminal;

selectively coupling the first voltage to at least one memory cell from the plurality of memory cells during an active state; and

selectively coupling the second voltage to at least one memory cell from the plurality of memory cells during an idle state;

wherein:

during a predetermined time cycle, the plurality of memory cells operate in the active state and the idle state; and

the predetermined time cycle is equal to an inverse of the sampling frequency.

11. The method for operating a system according to claim 10 , wherein:

the first voltage is less than a maximum operating voltage of the plurality of memory cells and greater than a minimum operating voltage of the plurality of memory cells; and

the second voltage is less than the minimum operating voltage of the plurality of memory cells and greater than a minimum retention voltage of the plurality of memory cells.

12. The method for operating a system according to claim 10 , wherein

the plurality of memory cells operate in the active state during a first predetermined time segment;

the plurality of memory cells operate in the idle state during a second predetermined time segment; and

the sum of the first predetermined time segment and the second predetermined time segment is equal to the predetermined time cycle.

13. The method for operating a system according to claim 12 , the first predetermined time segment is equal to the inverse of the clock frequency.

14. The method for operating a system according to claim 10 , wherein the sampling frequency is selected according to a range of human hearing.

15. An audio system capable of receiving power from a power supply, comprising:

a CPU configured to generate a clock signal having a clock frequency based on a sampling frequency, wherein the sampling frequency is selected according to a range of human hearing;

a voltage control circuit coupled to the CPU and configured to:

receive the sampling frequency; and

output a voltage control signal according to the sampling frequency;

a voltage generator configured to:

couple to the power supply; and

generate:

a first voltage at a first output; and

a second voltage at a second output;

a selector circuit coupled to an output of the voltage control circuit and the first and second outputs of the voltage generator, wherein the selector circuit selectively outputs, at an output terminal, one of the first voltage and the second voltage according to the voltage control signal; and

a processing system coupled to the output terminal of the selector circuit, comprising a plurality of data processing circuits, each comprising a memory cell configured to operate in an active state and in an idle state, wherein the selector circuit outputs:

the first voltage substantially coincident with the active state; and

the second voltage substantially coincident with the idle state.

16. The audio system according to claim 15 , wherein:

the voltage control signal comprises a first control signal and a second control signal; and

the voltage control circuit outputs:

the first control signal for a first predetermined time segment; and

the second control signal for a second predetermined time segment.

17. The audio system according to claim 16 , wherein:

a sum of the first and second time segments equal a predetermined time cycle; and

the time cycle is equal to an inverse of the sampling frequency.

18. The audio system according to claim 16 , wherein the first predetermined time segment is equal to an inverse of the clock frequency.

19. The audio system according to claim 16 , wherein:

during the first predetermined time segment, the memory cell operates in the active state and the selector circuit couples the first voltage to the memory cell; and

during the second predetermined time segment, the memory cell operates in the idle state and the selector circuit couples the second voltage to the memory cell.

20. The audio system according to claim 15 , wherein:

when the memory cell operates in the active state, the memory cell is capable of reading and writing data; and

when the memory cell operates in the idle state, the memory cell is:

capable of retaining previously-written data; and

incapable of reading and writing new data.