IP Library Granted Patent US 10,289,555
Granted Patent B1
US 10,289,555 · App. 15/488,025 · Granted May 14, 2019

Memory read-ahead using learned memory access patterns

Inventors: Adrian Michaud (Carlisle, MA); Kenneth J. Taylor (Franklin, MA); Randall Shain (Wrentham, MA); Stephen Wing-Kin Au (Norwood, MA); Junping Zhao (Beijing, CN)
Assignee: EMC IP Holding Company LLC
G06F12/0862G06F12/1009G06F2212/6026G06F2212/657
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Quick Facts
Patent No.
US 10,289,555
App. No.
15/488,025
Granted
May 14, 2019
Kind
B1
Abstract

Systems, methods, and articles of manufacture comprising processor-readable storage media are provided to implement read-ahead memory operations using learned memory access patterns for memory management systems. For example, a method for managing memory includes receiving a request from requestor (e.g., an active process) to perform a memory access operation, which includes a requested memory address. A determination is made as to whether a data block (e.g., page) associated with the requested memory address resides in a cache memory. When the data block associated with the requested memory address is not in the cache memory, a memory read-ahead process is performed which includes identifying a learned memory access pattern associated with the requestor, wherein the learned memory access pattern includes a plurality of data blocks starting with the data block associated with the requested memory address, and prefetching the plurality of data blocks associated with the learned memory access pattern into the cache memory.

Claims (64)

1. A method for managing memory, comprising:

receiving a request from a requesting entity to perform a memory access operation, wherein the received request comprises a requested memory address;

determining if a data block associated with the requested memory address resides in a cache memory;

accessing the data block from the cache memory in response to the received request, when the data block associated with the requested memory address is determined to reside in the cache memory;

performing a memory read-ahead process when the data block associated with the requested memory address is determined to not reside in the cache memory, wherein the memory read-ahead process comprises:

detecting a repeatable memory access pattern associated with the requesting entity, which comprises a plurality of data blocks starting with the data block associated with the requested memory address; and

prefetching the plurality of data blocks associated with the detected repeatable memory access pattern into the cache memory; and

restarting the memory access operation starting with the data block associated with the requested memory address, which is prefetched into the cache memory;

wherein detecting the repeatable memory access pattern associated with the requesting entity comprises:

determining a requestor ID of the requesting entity;

accessing a database of memory access metadata which comprises data block access metadata associated with the requestor ID; and

utilizing the data block access metadata associated with the requestor ID to determine the plurality of data blocks of the repeatable memory access pattern starting with the data block associated with the requested memory address, which are frequently accessed by the requesting entity with the requestor ID; and

wherein the data block access metadata for a given data block comprises access count metadata which provides an indication of a next data block that is frequently accessed by the requesting entity following the given data block, based on a comparison of the access count metadata to a predefined access count threshold value.

2. The method of claim 1 , wherein the method is implemented by a virtual memory management system, wherein the data blocks comprise pages, wherein the requesting entity comprises an active process issuing requests for pages in a virtual address space of the active process, and wherein the cache memory comprises a page cache maintained in system memory.

3. The method of claim 1 , further comprising storing the detected repeatable memory access pattern in a database of learned memory access patterns.

4. The method of claim 3 , wherein the database of learned memory access patterns comprises one or more different repeatable memory access patterns which are learned from historical memory access requests of the requesting entity.

5. The method of claim 1 , wherein utilizing the data block access metadata associated with the requestor ID to determine the plurality of data blocks starting with the data block associated with the requested memory address, which are frequently accessed by the requesting entity with the requestor ID comprises analyzing the data block metadata to detect a non-sequential pattern of data blocks which are determined to have been repeatedly accessed by the requesting entity for a predefined number of times by comparison to the predefined access count threshold value.

6. The method of claim 1 , wherein utilizing the data block access metadata associated with the requestor ID to determine the plurality of data blocks starting with the data block associated with the requested memory address, which are frequently accessed by the requesting entity with the requestor ID comprises analyzing the data block metadata to detect a sequential pattern of data blocks which are determined to have been repeatedly accessed by the requesting entity for a predefined number of times by comparison to the predefined access count threshold value.

7. The method of claim 1 , wherein the memory access metadata comprises:

a data block request metadata structure that is maintained for each data block that has been accessed by the requesting entity, wherein the data block request metadata structure for a given data block is indexed by a data block request identifier (ID) associated with the given data block; and

global metadata associated with the requesting entity, wherein the global metadata is indexed by a requestor ID assigned to the requesting entity.

8. The method of claim 7 , wherein the data block request metadata structure for the memory request ID of a given data block comprises a plurality of rows of metadata, wherein each row of metadata comprises (i) a requestor ID entry which identifies a requesting entity that has accessed the given data block, (ii) a next data block entry which identifies a next data block that the requesting entity has accessed following the given data block, (iii) a timestamp value which indicates a time that the next data block was last accessed, and (iv) a counter value as the access count metadata which indicates a number of times the next data block has been accessed following the given data block associated with the data block request metadata structure.

9. The method of claim 8 , wherein the requesting entity comprises an active process, wherein the given data block comprises a virtual page, wherein the requestor ID comprises a unique process ID that is assigned to the active process, and wherein the memory request ID comprises a page frame number (PFN).

10. The method of claim 7 , wherein the global metadata associated with the requesting entity comprises (i) a previous data block entry which identifies a previous data block that was last accessed by the requesting entity, and (ii) a timestamp value which indicates a time that the previous data block was last accessed by the requesting entity.

11. An article of manufacture comprising a non-transitory processor-readable storage medium having stored therein program code of one or more software programs, wherein the program code is executable by one or more processors to perform a method comprising:

receiving a request from a requesting entity to perform a memory access operation, wherein the received request comprises a requested memory address;

determining if a data block associated with the requested memory address resides in a cache memory;

accessing the data block from the cache memory in response to the received request, when the data block associated with the requested memory address is determined to reside in the cache memory;

performing a memory read-ahead process when the data block associated with the requested memory address is determined to not reside in the cache memory, wherein the memory read-ahead process comprises:

detecting a repeatable memory access pattern associated with the requesting entity, which comprises a plurality of data blocks starting with the data block associated with the requested memory address; and

prefetching the plurality of data blocks associated with the detected repeatable memory access pattern into the cache memory; and

restarting the memory access operation starting with the data block associated with the requested memory address, which is prefetched into the cache memory;

wherein detecting the repeatable memory access pattern associated with the requesting entity comprises:

determining a requestor ID of the requesting entity;

accessing a database of memory access metadata which comprises data block access metadata associated with the requestor ID; and

utilizing the data block access metadata associated with the requestor ID to determine the plurality of data blocks of the repeatable memory access pattern starting with the data block associated with the requested memory address, which are frequently accessed by the requesting entity with the requestor ID; and

wherein the data block access metadata for a given data block comprises access count metadata which provides an indication of a next data block that is frequently accessed by the requesting entity following the given data block, based on a comparison of the access count metadata to a predefined access count threshold value.

12. The article of manufacture of claim 11 , wherein the method is implemented by a virtual memory management system, wherein the data blocks comprise pages, wherein the requesting entity comprises an active process issuing requests for pages in the virtual address space of the active process, and wherein the cache memory comprises a page cache maintained in system memory.

13. The article of manufacture of claim 11 , further comprising storing the detected repeatable memory access pattern in a database of learned memory access patterns.

14. The article of manufacture of claim 13 , wherein the database of learned memory access patterns comprises one or more different repeatable memory access patterns which are learned from historical memory access requests of the requesting entity.

15. The article of manufacture of claim 11 , wherein utilizing the data block access metadata associated with the requestor ID to determine the plurality of data blocks starting with the data block associated with the requested memory address, which are frequently accessed by the requesting entity with the requestor ID comprises analyzing the data block metadata to detect at least one of a sequential and a non-sequential pattern of data blocks which are determined to have been repeatedly accessed by the requesting entity for a predefined number of times by comparison to the predefined access count threshold value.

16. The article of manufacture of claim 11 , wherein the memory access metadata comprises:

a data block request metadata structure that is maintained for each data block that has been accessed by the requesting entity, wherein the data block request metadata structure for a given data block is indexed by a data block request identifier (ID) associated with the given data block; and

global metadata associated with the requesting entity, wherein the global metadata is indexed by a requestor ID assigned to the requesting entity;

wherein the data block request metadata structure for the memory request ID of a given data block comprises a plurality of rows of metadata, wherein each row of metadata comprises (i) a requestor ID entry which identifies a requesting entity that has accessed the given data block, (ii) a next data block entry which identifies a next data block that the requesting entity has accessed following the given data block, (iii) a timestamp value which indicates a time that the next data block was last accessed, and (iv) a counter value as the access count metadata which indicates a number of times the next data block has been accessed following the given data block associated with the memory request metadata structure; and

wherein the global metadata associated with the requesting entity comprises (i) a previous data block entry which identifies a previous data block that was last accessed by the requesting entity, and (ii) a timestamp value which indicates a time that the previous data block was last accessed by the requesting entity.

17. A system, comprising:

at least one processor; and

memory to store program instructions that are executed by the at least one processor to perform a method comprising:

receiving a request from a requesting entity to perform a memory access operation, wherein the received request comprises a requested memory address;

determining if a data block associated with the requested memory address resides in a cache memory;

accessing the data block from the cache memory in response to the received request, when the data block associated with the requested memory address is determined to reside in the cache memory;

performing a memory read-ahead process when the data block associated with the requested memory address is determined to not reside in the cache memory, wherein the memory read-ahead process comprises:

detecting a repeatable memory access pattern associated with the requesting entity, which comprises a plurality of data blocks starting with the data block associated with the requested memory address; and

prefetching the plurality of data blocks associated with the detected repeatable memory access pattern into the cache memory; and

restarting the memory access operation starting with the data block associated with the requested memory address, which is prefetched into the cache memory;

wherein detecting the repeatable memory access pattern associated with the requesting entity comprises:

determining a requestor ID of the requesting entity;

accessing a database of memory access metadata which comprises data block access metadata associated with the requestor ID; and

utilizing the data block access metadata associated with the requestor ID to determine the plurality of data blocks of the repeatable memory access pattern starting with the data block associated with the requested memory address, which are frequently accessed by the requesting entity with the requestor ID; and

wherein the data block access metadata for a given data block comprises access count metadata which provides an indication of a next data block that is frequently accessed by the requesting entity following the given data block, based on a comparison of the access count metadata to a predefined access count threshold value.

18. The system of claim 17 , wherein the system comprises a virtual memory management system, wherein the data blocks comprise pages, wherein the requesting entity comprises an active process issuing requests for pages in the virtual address space of the active process, and wherein the cache memory comprises a page cache maintained in system memory.

19. The system of claim 17 , wherein the detected repeatable memory access pattern is stored in a database of learned memory access patterns.

20. The system of claim 17 , wherein utilizing the data block access metadata associated with the requestor ID to determine the plurality of data blocks starting with the data block associated with the requested memory address, which are frequently accessed by the requesting entity with the requestor ID comprises analyzing the data block metadata to detect at least one of a sequential and a non-sequential pattern of data blocks which are determined to have been repeatedly accessed by the requesting entity for a predefined number of times by comparison to the predefined access count threshold value.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (042769/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0802 →
RELEASE OF SECURITY INTEREST AT REEL 042768 FRAME 0585 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0536 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2017
From: MICHAUD, ADRIAN; TAYLOR, KENNETH J.; SHAIN, RANDALL; AU, STEPHEN WING-KIN; ZHAO, JUNPING
To: EMC IP HOLDING COMPANY LLC
Reel/Frame 043239/0745 →
PATENT SECURITY INTEREST (CREDIT) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 042768/0585 →
PATENT SECURITY INTEREST (NOTES) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 042769/0001 →
Cited By (8)
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