IP Library › Granted Patent US 10,332,302
Granted Patent B2
US 10,332,302 · App. 15/489,090 · Granted Jun 25, 2019

Scatter gather engine

Inventors: Balaji Vembu (Folsom, CA); Murali Ramadoss (Folsom, CA); David I. Standring (Mather, CA); Shruti A. Sethi (Folsom, CA); Jeffrey S. Frizzell (Folsom, CA); Alan M. Curtis (Folsom, CA); Abhishek R. Appu (El Dorado Hills, CA); Joydeep Ray (Folsom, CA); Altug Koker (El Dorado Hills, CA)
Assignee: INTEL CORPORATION
G06T15/005G06F12/023G06F2212/1044
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Quick Facts
Patent No.
US 10,332,302
App. No.
15/489,090
Granted
Jun 25, 2019
Kind
B2
Abstract

In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.

Claims (61)

1. An apparatus comprising:

a processor comprising a plurality of execution units, the processor to:

create a scatter gather list in a memory;

collect a plurality of operating statistics for the plurality of execution units using the scatter gather list;

create a list of register addresses in the memory;

allocate a space in the memory for an output of the register addresses;

cause a first register to point to a descriptor;

cause a second register to point to an output address; and

configure a third register with a poll period, a number of iterations, and an interrupt enable/disable.

2. The apparatus of claim 1 , the processor to:

start the scatter gather engine by setting a ScatterGatherControlStart_Gather.

3. The apparatus of claim 2 , the processor to:

stop the scatter gather engine by resetting the ScatterGatherControlStart_Gather.

4. The apparatus of claim 1 , the processor to:

inspect the status of the scatter gather data collection in a scatter gather control register.

5. The apparatus of claim 1 , wherein the memory comprises a static random access memory.

6. The apparatus of claim 1 , wherein the plurality of execution units are on a single integrated circuit.

7. The apparatus of claim 1 , wherein:

the first register is a scatter gather source attributes register;

the second register is a scatter gather description destination attributes register; and

the third register is a scatter gather description configuration register.

8. A non-transitory computer-readable medium comprising logic instructions which, when executed by a processor comprising a plurality of execution units, configure the processor to:

create a scatter gather list in a memory;

collect a plurality of operating statistics for the plurality of execution units using the scatter gather list;

create a list of register addresses in the memory;

allocate a space in the memory for an output of the register addresses;

cause a first register to point to a descriptor;

cause a second register to point to an output address; and

configure a third register with a poll period, a number of iterations, and an interrupt enable/disable.

9. The non-transitory computer-readable medium of claim 8 , wherein the instructions configure the processor to:

start the scatter gather engine by setting a ScatterGatherControlStart_Gather.

10. The non-transitory computer-readable medium of claim 9 , wherein the instructions configure the processor to:

stop the scatter gather engine by resetting the ScatterGatherControlStart_Gather.

11. The non-transitory computer-readable medium of claim 8 , wherein the instructions configure the processor to:

inspect the status of the scatter gather data collection in a scatter gather control register.

12. The non-transitory computer-readable medium of claim 8 , wherein the memory comprises a static random access memory.

13. The non-transitory computer-readable medium of claim 8 , wherein the plurality of execution units are on a single integrated circuit.

14. The non-transitory computer-readable medium of claim 8 , wherein:

the first register is a scatter gather source attributes register;

the second register is a scatter gather description destination attributes register; and

the third register is a scatter gather description configuration register.

15. A method comprising:

creating, on a processor comprising a plurality of execution units, a scatter gather list in a memory;

collecting a plurality of operating statistics for the plurality of execution units using the scatter gather list;

creating a list of register addresses in the memory;

allocating a space in the memory for an output of the register addresses;

causing a first register to point to a descriptor;

causing a second register to point to an output address; and

configuring a third register with a poll period, a number of iterations, and an interrupt enable/disable.

16. The method of claim 15 , further comprising:

start the scatter gather engine by setting a ScatterGatherControlStart_Gather.

17. The method of claim 16 , further comprising:

stop the scatter gather engine by resetting the ScatterGatherControlStart_Gather.

18. The method of claim 15 , further comprising:

inspect the status of the scatter gather data collection in a scatter gather control register.

19. The method of claim 15 , wherein the memory comprises a static random access memory.

20. The method of claim 15 , wherein the plurality of execution units are on a single integrated circuit.

21. The method of claim 15 , wherein:

the first register is a scatter gather source attributes register;

the second register is a scatter gather description destination attributes register; and

the third register is a scatter gather description configuration register.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2017
From: VEMBU, BALAJI; RAMADOSS, MURALI; STANDRING, DAVID I.; SETHI, SHRUTI A.; FRIZZELL, JEFFREY S.; CURTIS, ALAN M.; APPU, ABHISHEK R.; RAY, JOYDEEP; KOKER, ALTUG
To: INTEL CORPORATION
Reel/Frame 042618/0342 →
Continuity (1)
Related Publication 20180300931A1 · Oct 18, 2018