IP Library › Granted Patent US 10,672,175
Granted Patent B2
US 10,672,175 · App. 15/489,177 · Granted Jun 2, 2020

Order independent asynchronous compute and streaming for graphics

Inventors: Devan Burke (Portland, OR); Adam T. Lake (Portland, OR); Jeffery S. Boles (Folsom, CA); John H. Feit (Folsom, CA); Karthik Vaidyanathan (Berkeley, CA); Abhishek R. Appu (El Dorado Hills, CA); Joydeep Ray (Folsom, CA); Subramaniam Maiyuran (Gold River, CA); Altug Koker (El Dorado Hills, CA); Balaji Vembu (Folsom, CA); Murali Ramadoss (Folsom, CA); Prasoonkumar Surti (Folsom, CA); Eric J. Hoekstra (Latrobe, CA); Gabor Liktor (San Francisco, CA); Jonathan Kennedy (Bristol, GB); Slawomir Grajewski (Gdansk, PL); Elmoustapha Ould-Ahmed-Vall (Chandler, AZ)
Assignee: Intel Corporation
G06T15/005G06F9/4881G06T15/04G06T15/80G06T17/10G06T17/20
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Quick Facts
Patent No.
US 10,672,175
App. No.
15/489,177
Granted
Jun 2, 2020
Kind
B2
Abstract

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

Claims (57)

1. A computing system for graphics data processing, the computing system comprising:

one or more processors; and

a memory coupled to the one or more processors, the memory including executable program instructions, which when executed by the host processor, cause the computing system to:

determine an order dependency between two or more draw calls;

re-order the two or more draw calls based on the determined order dependency;

re-order two or more work items in an order independent mode, wherein the order independent mode is made in response to a guarantee of memory dependency, when the guarantee is made for a particular phase of rendering in a first mode of operation and for an entire application in a different second mode of operation;

define a producer stage and a consumer stage after performing the re-order of the two or more draw calls;

provide tile-based order independent execution of a compute stage; and

perform a full screen resolve pass to resolve one or more out-of-order issues caused in the order independent mode, wherein the full screen resolve pass is performed after performance of the tile-based order independent execution of the compute stage.

2. The system of claim 1 , wherein the re-order of two or more work items includes operations to:

determine a work split for the two or more work items, and re-order the two or more work items based on the determined work split.

3. The system of claim 1 , wherein the executable program instructions, when executed by the computing system, cause the computing system to:

alternate execution of the producer stage and the consumer stage in accordance with the queue primitive.

4. The system of claim 1 , wherein the provision of tile-based order independent execution includes operations to:

dispatch work asynchronously on a tile basis to a render context and a compute context.

5. A semiconductor apparatus for graphics data processing, the semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

determine an order dependency between two or more draw calls;

re-order the two or more draw calls based on the determined order dependency;

re-order two or more work items in an order independent mode, wherein the order independent mode is made in response to a guarantee of memory dependency, when the guarantee is made for a particular phase of rendering in a first mode of operation and for an entire application in a different second mode of operation; and

perform a full screen resolve pass to resolve one or more out-of-order issues caused in the order independent mode, wherein the full screen resolve pass is performed after performance of a tile-based order independent execution of a compute stage.

6. The apparatus of claim 5 , wherein the determination of the order dependency further includes operations to determine a resource requirement and data address range for the two or more draw calls.

7. The apparatus of claim 5 , wherein the re-order of the two or more draw calls further includes operations to re-order the two or more draw calls to increase a utilization of parallel execution.

8. The apparatus of claim 7 , wherein the re-order of the two or more draw calls further includes operations to determine that no data dependency is violated when the two or more draw calls are re-ordered.

9. The apparatus of claim 5 , wherein the logic coupled to the one or more substrates is further to:

define a producer stage and a consumer stage after performing the re-order of the two or more draw calls.

10. The apparatus of claim 5 , wherein the logic coupled to the one or more substrates is further to:

provide tile-based order independent execution of a compute stage.

11. A method of re-ordering draw calls, comprising:

determining an order dependency between two or more draw calls; and

re-ordering the two or more draw calls based on the determined order dependency;

re-ordering two or more work items in an order independent mode, wherein the order independent mode is made in response to a guarantee of memory dependency, when the guarantee is made for a particular phase of rendering in a first mode of operation and for an entire application in a different second mode of operation; and

performing a full screen resolve pass to resolve one or more out-of-order issues caused in the order independent mode, wherein the full screen resolve pass is performed after performance of a tile-based order independent execution of a compute stage.

12. The method of claim 11 , further comprising:

determining a resource requirement and data address range for the two or more draw calls.

13. The method of claim 11 , further comprising:

re-ordering the two or more draw calls to increase a utilization of parallel execution.

14. The method of claim 13 , further comprising:

determining that no data dependency is violated when the two or more draw calls are re-ordered.

15. The method of claim 11 , further comprising:

defining a producer stage and a consumer stage with a queue primitive after performing the re-order of the two or more draw calls.

16. The method of claim 11 , further comprising:

providing tile-based order independent execution of a compute stage.

17. At least one non-transitory computer readable medium, comprising a set of instructions, which when executed by a computing device cause the computing device to:

determine an order dependency between two or more draw calls; and

re-order the two or more draw calls based on the determined order dependency;

re-order two or more work items in an order independent mode, wherein the order independent mode is made in response to a guarantee of memory dependency, when the guarantee is made for a particular phase of rendering in a first mode of operation and for an entire application in a different second mode of operation; and

perform a full screen resolve pass to resolve one or more out-of-order issues caused in the order independent mode, wherein the full screen resolve pass is performed after performance of a tile-based order independent execution of a compute stage.

18. The at least one non-transitory computer readable medium of claim 17 , comprising a further set of instructions, which when executed by a computing device cause the computing device to:

determine a resource requirement and data address range for the two or more draw calls.

19. The at least one non-transitory computer readable medium of claim 17 , comprising a further set of instructions, which when executed by a computing device cause the computing device to:

re-order the two or more draw calls to increase a utilization of parallel execution.

20. The at least one non-transitory computer readable medium of claim 19 , comprising a further set of instructions, which when executed by a computing device cause the computing device to:

determine that no data dependency is violated when the two or more draw calls are re-ordered.

21. The at least one non-transitory computer readable medium of claim 17 , comprising a further set of instructions, which when executed by a computing device cause the computing device to:

define a producer stage and a consumer stage with a queue primitive primitive after performing the re-order of the two or more draw calls.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2020
From: BURKE, DEVAN; LAKE, ADAM T.; BOLES, JEFFERY S.; FEIT, JOHN H.; VAIDYANATHAN, KARTHIK; APPU, ABHISHEK R.; RAY, JOYDEEP; MAIYURAN, SUBRAMANIAM; KOKER, ALTUG; VEMBU, BALAJI; RAMADOSS, MURALI; SURTI, PRASOONKUMAR; HOEKSTRA, ERIC J.; LIKTOR, GABOR; KENNEDY, JONATHAN; GRAJEWSKI, SLAWOMIR; OULD-AHMED-VALL, ELMOUSTAPHA
To: INTEL CORPORATION
Reel/Frame 053283/0900 →
Continuity (1)
Related Publication 20180300933A1 · Oct 18, 2018
Cited By (1)
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