3D cross-bar nonvolatile memory
Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
1. A method of forming a nonvolatile memory structure, the method comprising:
forming a plurality of heavily-doped nanowire structures on a substrate with a plurality of transistors;
forming a charge-trapping stack of layers on the plurality of heavily-doped nanowire structures;
forming a plurality of gate electrodes on the charge-trapping stack of layers;
forming a first interconnect between a first heavily-doped nanowire structure of the plurality of heavily-doped nanowire structures and a first transistor; and
forming a second interconnect between a first gate electrode of the plurality of gate electrodes and a second transistor.
2. The method of claim 1 , wherein forming the plurality of heavily-doped nanowire structures comprises:
growing a semiconductor layer;
disposing the semiconductor layer on the substrate; and
patterning the semiconductor layer.
3. The method of claim 2 , further comprising implanting at least one dopant species into the semiconductor layer to form a heavily-doped semiconductor layer prior to disposing the semiconductor layer on the substrate.
4. The method of claim 3 , wherein the heavily-doped semiconductor layer has an n-doped concentration between 5×10 18 atoms/cm 3 and 5×10 19 atoms/cm 3 .
5. The method of claim 3 , wherein the heavily-doped semiconductor layer has a p-doped concentration between 5×10 18 atoms/cm 3 and 5×10 19 atoms/cm 3 .
6. The method of claim 2 , wherein growing the semiconductor layer comprises epitaxially growing silicon.
7. The method of claim 2 , wherein growing the semiconductor layer comprises epitaxially growing silicon germanium.
8. The method of claim 1 , wherein forming the first and second interconnects comprises etching respective first and second openings in the substrate.
9. The method of claim 1 , wherein forming the charge-trapping stack of layers comprises:
depositing a first oxide layer on each heavily-doped nanowire structure;
depositing a nitride layer on the first oxide layer; and
depositing a second oxide layer on the nitride layer.
10. The method of claim 1 , wherein the plurality of gate electrodes are arranged in a plurality of rows perpendicularly-oriented to the plurality of heavily-doped nanowire structures.
11. A method of forming a nonvolatile memory, the method comprising:
forming a plurality of doped crystalline semiconductor structures;
forming a plurality of gate structures around each of the plurality of doped crystalline semiconductor structures;
forming a first interconnect to electrically couple a first doped crystalline semiconductor structure of the plurality of doped crystalline semiconductor structures to a first transistor; and
forming a second interconnect to electrically couple a first gate structure of the plurality of gate structures to a second transistor.
12. The method of claim 11 , wherein the doped crystalline semiconductor layer has an n-doped concentration between 5×10 18 atoms/cm 3 and 5×10 19 atoms/cm 3 .
13. The method of claim 11 , wherein the doped crystalline semiconductor layer has a p-doped concentration between 5×10 18 atoms/cm 3 and 5×10 19 atoms/cm 3 .
14. The method of claim 11 , wherein forming the plurality of gate structures comprises depositing an oxide-nitride-oxide charge-trapping stack over the plurality of doped crystalline semiconductor structures.
15. The method of claim 14 , wherein forming the plurality of gate structures further comprises:
depositing a gate electrode layer over the oxide-nitride-oxide charge-trapping stack; and
patterning the gate electrode layer.
16. A nonvolatile memory structure comprising:
a plurality of doped crystalline semiconductor structures;
a plurality of gate structures around each of the plurality of doped crystalline semiconductor structures;
a first interconnect electrically coupling a first doped crystalline semiconductor structure of the plurality of doped crystalline semiconductor structures and a first transistor; and
a second interconnect electrically coupling a first gate structure of the plurality of gate structures and a second transistor.
17. The nonvolatile memory structure of claim 16 , wherein a first gate structure of the plurality of gate structures comprises a charge-trapping gate dielectric stack and an electrically conductive gate electrode on the charge-trapping gate dielectric stack.
18. The nonvolatile memory structure of claim 17 , wherein the plurality of doped crystalline semiconductor structures are arranged in a plurality of columns and the plurality of gate structures are arranged in a plurality of rows.
19. The nonvolatile memory structure of claim 16 , further comprising a second gate structure of the plurality of gate structures and a second doped crystalline semiconductor structure of the plurality of doped crystalline semiconductor structures, wherein the second gate structure is on the first and second doped crystalline semiconductor structures.
20. The nonvolatile memory structure of claim 16 , wherein the first doped crystalline semiconductor structure has an n-doped concentration between 5×10 18 atoms/cm 3 and 5×10 19 atoms/cm 3 .