Compact three-dimensional memory with an above-substrate decoding stage
The above-substrate decoding stage of a compact three-dimensional memory (3D-M c ) could be an intra-level decoding stage, an inter-level decoding stage, or a combination thereof. For the intra-level decoding stage, contact vias can be shared by address-lines in the same memory level; for the inter-level decoding stage, contact vias can be shared by address-lines from different memory levels.
1. A compact three-dimensional memory (3D-M c ), comprising:
a semiconductor substrate with transistors thereon;
a memory level stacked above said semiconductor substrate, said memory level comprising at least a memory array and at least an intra-level decoding stage; and
at least a contact via coupling said memory level with said semiconductor substrate;
wherein said memory array comprises:
a plurality of parallel x-lines including first and second x-lines extending from said memory array to said intra-level decoding stage;
a plurality of parallel y-lines intersecting said x-lines;
a plurality of memory devices located at the intersections of said x-lines and said y-lines, each of said memory devices comprising a diode or a diode-like device;
said intra-level decoding stage comprises:
a plurality of parallel control-lines (c-lines) including first and second c-lines intersecting said x-lines;
a plurality of decoding devices including first and second decoding devices, said first decoding device being located at the intersection of said first x-line and said first c-line; and, said second decoding device being located at the intersection of said second x-line and said second c-line; each of said decoding devices comprising a transistor or a transistor-like device;
wherein said intra-level decoding stage has first and second modes: in said first mode, said first x-line is electrically coupled to said contact via by switching on said first decoding device and switching off said second decoding device; in said second mode, said second x-line is electrically coupled to said contact via by switching off said first decoding device and switching on said second decoding device.
2. The memory according to claim 1 , wherein each of said memory devices is a two-terminal device.
3. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM).
4. The memory according to claim 1 , wherein said 3D-M comprises a three-dimensional random-access memory (3D-RAM).
5. The memory according to claim 1 , wherein the overlap portion of the x-line with the c-line in each of said decoding devices is semi-conductive.
6. The memory according to claim 1 , wherein the non-overlap portions of the x-line with the c-line in each of said decoding devices are highly-conductive.
7. The memory according to claim 1 , wherein each of said decoding devices is a three-terminal device.
8. The memory according to claim 1 , wherein each of said decoding devices comprises a pass-transistor.
9. The memory according to claim 1 , wherein each of said decoding devices comprises a MOSFET.
10. The memory according to claim 1 , wherein each of said decoding devices comprises a JFET.
11. A compact three-dimensional memory (3D-M c ) with an inter-level decoding stage, comprising:
a semiconductor substrate with transistors thereon;
a first memory level stacked above said semiconductor substrate, said first memory level comprising at least a first memory array and at least a first portion of said inter-level decoding stage;
a second memory level stacked above said first memory level, said second memory level comprising at least a second memory array and at least a second portion of said inter-level decoding stage; and
at least a contact via coupling said first and second memory levels with said semiconductor substrate;
wherein said first memory array comprises a first x-line extending from said first memory array to said first portion of said inter-level decoding stage; a first y-line intersecting said first x-line; and, a first memory device located at the intersection of said first x-line and said first y-line;
said first portion of said inter-level decoding stage comprises a first control-line (c-line) intersecting said first x-line; and, a first decoding device located at the intersection of said first x-line and said first x-line;
said second memory array comprises a second x-line extending from said second memory array to said second portion of said inter-level decoding stage; a second y-line intersecting said second x-line; and, a second memory device located at the intersection of said second x-line and said second y-line;
said second portion of said inter-level decoding stage comprises a second c-line intersecting said second x-line; and, a second decoding device located at the intersection of said second x-line and said second c-line;
wherein said inter-level decoding stage has first and second modes: in said first mode, said first x-line is electrically coupled to said contact via by switching on said first decoding device and switching off said second decoding device; in said second mode, said second x-line is electrically coupled to said contact via by switching off said first decoding device and switching on said second decoding device.
12. The memory according to claim 11 , wherein each of said first and second memory devices comprising a diode or a diode-like device.
13. The memory according to claim 12 , wherein the overlap portion and the non-overlap portions of the x-line with the y-line in each of said first and second memory devices are both highly-conductive.
14. The memory according to claim 11 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM).
15. The memory according to claim 11 , wherein said 3D-M comprises a three-dimensional random-access memory (3D-RAM).
16. The memory according to claim 11 , wherein
the overlap portion of the x-line with the c-line in each of said first and second decoding devices is semi-conductive; and,
the non-overlap portions of the x-line with the c-line in each of said first and second decoding devices are highly-conductive.
17. The memory according to claim 11 , wherein each of said first and second decoding devices comprises a transistor or a transistor-like device.
18. The memory according to claim 11 , wherein each of said first and second decoding devices comprises a pass-transistor.
19. The memory according to claim 11 , wherein each of said first and second decoding devices comprises a MOSFET.
20. The memory according to claim 11 , wherein each of said first and second decoding devices comprises a JFET.