Semiconductor packages having asymmetric chip stack structure
A semiconductor package may include first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall. The semiconductor package may include a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall. The first protrusion corner of the first chip stack may protrude toward the second chip stack.
1. A semiconductor package comprising:
a first chip stack including first chips which are stacked on a package substrate and offset in a first offset direction; and
a second chip stack including second chips which are stacked on the package substrate and offset in a second offset direction corresponding to an opposite direction to the first offset direction,
wherein a first protrusion corner of the first chip stack protruding toward the second chip stack vertically overlaps with a second protrusion corner of the second chip stack protruding toward the first chip stack, and
wherein the first chip stack and the second chip stack are laterally aligned.
2. The semiconductor package of claim 1 , further comprising an encapsulant covering the first and second chip stacks,
wherein the first chip stack is disposed so that a first forward stepwise sidewall of the first chip stack faces a first sidewall of the encapsulant, and a first reverse stepwise sidewall of the first chip stack opposite to the first forward stepwise sidewall faces the second chip stack; and
wherein the second chip stack is disposed so that a second forward stepwise sidewall of the second chip stack faces a second sidewall of the encapsulant opposite to the first sidewall, and a second reverse stepwise sidewall of the second chip stack opposite to the second forward stepwise sidewall faces the first reverse stepwise sidewall of the first chip stack.
3. The semiconductor package of claim 2 , wherein the second chip stack is disposed so that the second protrusion corner of the second chip stack faces the first reverse stepwise sidewall of the first chip stack.
4. The semiconductor package of claim 1 , further comprising:
a first bonding wire electrically connecting the package substrate to the first chips; and
a second bonding wire electrically connecting the package substrate to the second chips,
wherein the first bonding wire is disposed on a sidewall of the first chip stack opposite to the second chip stack, and the second bonding wire is disposed on a sidewall of the second chip stack opposite to the first chip stack.
5. The semiconductor package of claim 4 , wherein the package substrate includes:
a substrate body;
a first chip connection pattern disposed on a first edge portion of the substrate body and connected to the first bonding wire; and
a second chip connection pattern disposed on a second edge portion of the substrate body opposite to the first edge portion and connected to the second bonding wire.
6. The semiconductor package of claim 1 , wherein a height of the second chip stack is less than a height of the first chip stack.
7. The semiconductor package of claim 1 , wherein at least one of the second chips has a thickness which is less than a thickness of any one of the first chips.
8. The semiconductor package of claim 1 , wherein the first chip stack is spaced apart from the second protrusion corner of the second chip stack.
9. A semiconductor package comprising:
a first chip stack including first chips which are stacked on a package substrate and offset to form a first reverse stepwise sidewall; and
a second chip stack including second chips which are stacked on the package substrate and offset to form a second reverse stepwise sidewall,
wherein a first protrusion corner of the first chip stack protruding toward the second chip stack vertically overlaps with a second protrusion corner of the second chip stack protruding toward the first chip stack, and
wherein the first chip stack and the second chip stack are laterally aligned.
10. The semiconductor package of claim 9 , wherein the second chip stack includes a second protrusion corner protruding toward the first protrusion corner.
11. The semiconductor package of claim 10 , wherein the first protrusion corner vertically overlaps with the second protrusion corner.
12. The semiconductor package of claim 9 , wherein the first protrusion corner protrudes toward the center of the package substrate.
13. The semiconductor package of claim 9 , wherein the first protrusion corner protrudes away from a first edge portion of the package substrate.
14. The semiconductor package of claim 13 , further comprising:
a first bonding wire electrically connecting the package substrate at the first edge portion to the first chips.
15. The semiconductor package of claim 9 , wherein at least one of the second chips has a thickness which is less than a thickness of any one of the first chips.
16. A semiconductor package comprising:
a first chip stack including first chips which are stacked on a package substrate and offset in a first offset direction;
a second chip stack including second chips which are stacked on the package substrate and offset in a second offset direction;
a first spacer disposed between two adjacent chips of the first chips; and
a second spacer disposed between two adjacent chips of the second chips,
wherein a first protrusion corner of the first chip stack protrudes toward the second chip stack with a second protrusion corner of the second chip stack protruding towards the first chip stack, and a thickness of the second spacer is different from a thickness of the first spacer.
17. The semiconductor package of claim 16 , wherein the number of first chips is equal to the number of second chips.
18. The semiconductor package of claim 16 , wherein the second protrusion corner of the second chip stack is spaced apart from the first spacer of the first chip stack to allow an encapsulant to flow into a space between the first and second chip stacks.