Static random access memory having insulating layer with different thicknesses
View Patent ↗A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region and the substrate includes a semiconductor layer on top of an insulating layer; forming a first front gate on the first region of the substrate and a second front gate on the second region of the substrate; removing part of the insulating layer under the first front gate; forming a first back gate on the insulating layer under the first front gate; and forming a second back gate under the second front gate.
1. A semiconductor device, comprising:
a substrate having a first region and a second region, wherein the substrate comprises a semiconductor layer on top of an insulating layer and the insulating layer contacts the semiconductor layer directly;
a first front gate electrode on the first region of the substrate and a second front gate electrode on the second region of the substrate, wherein a total thickness of the insulating layer directly under the first front gate electrode is different from a total thickness of the insulating layer directly under the second front gate electrode;
a first back gate on the insulating layer under the first front gate electrode; and
a second back gate on the insulating layer under the second front gate electrode.
2. The semiconductor device of claim 1 , further comprising:
a first dielectric layer on the substrate to cover the first front gate electrode and the second front gate electrode; and
first contact plugs in the first dielectric layer to electrically connect the first front gate electrode and the second front gate electrode.
3. The semiconductor device of claim 2 , further comprising:
a second dielectric layer on the insulating layer and adjacent to the first back gate.
4. The semiconductor device of claim 3 , wherein bottom surfaces of the second dielectric layer and the first back gate are coplanar.
5. The semiconductor device of claim 3 , further comprising a high-k dielectric layer on the second dielectric layer and the first back gate.
6. The semiconductor device of claim 1 , further comprising a third back gate under the first back gate, wherein bottom surfaces of the second back gate and the third gate are coplanar.
7. The semiconductor device of claim 6 , wherein the first back gate and the third back gate are disposed within the first region under the first front gate electrode.
8. The semiconductor device of claim 6 , wherein the first back gate contacts the third back gate directly.
9. The semiconductor device of claim 6 , further comprising:
a third dielectric layer on the second back gate and the third back gate;
a second contact plug on the second back gate; and
a fourth back gate on the second contact plug.
10. The semiconductor device of claim 9 , wherein the second back gate and the fourth back gate are disposed within the second region under the second front gate electrode.