Thermally stable salicide formation for salicide first contacts
A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
1. A semiconductor device, comprising:
epitaxially grown source/drain (S/D) regions each having a cross-sectional diamond quadrilateral shape formed on semiconductor fins on opposite sides of a transversely disposed gate structure, the S/D regions including to (111) facets on top halves of the cross-sectional diamond quadrilateral shapes, wherein epitaxial materials of adjacent ones of the S/D regions are separated in a non-merged configuration;
a silicide formed on the (111) facets on the top halves of the cross-sectional diamond quadrilateral shapes;
a dielectric layer formed over the S/D regions and the gate structure; and
contacts formed in respective contact holes through the dielectric layer to the silicide.
2. The device as recited in claim 1 , wherein the silicide is formed in a wrapped around configuration covering the top (111) facets and bottom (111) facets on bottom halves of the cross-sectional diamond quadrilateral shapes of the S/D regions.
3. The device as recited in claim 1 , wherein the silicide is formed continuously on the (11) facets of the S/D regions connecting the S/D regions.
4. The device as recited in claim 3 , wherein the contacts to the silicide formed on the (111) facets include partial contacts that skip contacting portions of the silicide corresponding to one or more of the S/D regions in a series of adjacent ones of the S/D regions to reduce capacitance.
5. The device as recited in claim 1 , wherein the silicide includes a metal selected from the group consisting of: Ti, Ta, Hf, Zr, Nb and combinations thereof.
6. The device as recited in claim 1 , wherein the gate structure includes a replacement metal gate (RMG).