IP Library Granted Patent US 10,446,193
Granted Patent B2
US 10,446,193 · App. 15/494,539 · Granted Oct 15, 2019

Mixed three-dimensional memory

Inventor: Guobiao Zhang (Corvallis, OR)
Assignees: Hangzhou HaiCun Information Technology Co., Ltd.; Guobiao Zhang
G11C5/025G11C8/12H01L27/0688H01L27/1128H01L27/11246H01L28/00H01L2224/32145H01L2224/73265H01L2924/00012
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Quick Facts
Patent No.
US 10,446,193
App. No.
15/494,539
Granted
Oct 15, 2019
Kind
B2
Abstract

The present invention discloses a mixed three-dimensional memory (3D-M x ). It comprises memory arrays (or, memory blocks) of different sizes. In a 3D-M x with mixed memory blocks, the memory blocks with different sizes are formed side-by-side. In a 3D-M x with mixed memory arrays, a plurality of small memory arrays are formed side-by-side underneath a single large memory array.

Claims (16)

1. A mixed three-dimensional memory (3D-M x ), comprising:

a first memory block, said first memory block comprising a first plurality of vertically stacked memory levels including a first topmost memory level, said first topmost memory level comprising a first memory array, said first memory array comprising first memory devices, each of said first memory devices sharing at least a first address-line with at least another one of said first memory devices;

a second memory block, said second memory block comprising a second plurality of vertically stacked memory levels including a second topmost level, said second topmost memory level comprising a second memory array, said second memory array comprising second memory devices, each of said second memory devices sharing at least a second address-line with at least another one of said second memory devices;

wherein, said second memory block is located side-by-side with said first memory block; said first topmost memory level is located at the same physical level with said second topmost memory level; and, said first memory array is physically larger and comprises more memory devices than said second memory array.

2. The memory according to claim 1 , wherein said first memory block stores data.

3. The memory according to claim 2 , wherein said data includes digital books, digital maps, digital music, digital movies, and/or digital videos.

4. The memory according to claim 1 , wherein said second memory block stores code.

5. The memory according to claim 4 , wherein said code includes operating system, software, and/or digital games.

6. A mixed three-dimensional memory (3D-M x ) comprising at least a 3D-M block, said 3D-M block further comprising a plurality of vertically stacked memory levels including a topmost memory level and at least an intermediate memory level, wherein:

said topmost memory level is the topmost memory level among all of said memory levels and comprises a first memory array, said first memory array comprising first memory devices, each of said first memory devices sharing at least a first address-line with at least another one of said first memory devices;

said intermediate memory level is a memory level below said topmost memory level and comprises at least second and third memory arrays, wherein said second memory array comprises second memory devices, each of said second memory devices sharing at least a second address-line with at least another one of said second memory devices; said third memory array comprises third memory devices, each of said third memory devices sharing at least a third address-line with at least another one of said third memory devices; and, said second and third memory arrays do not share any memory devices or address-lines;

wherein said first memory array fully covers both said second and third memory arrays; and, said first memory array is physically larger and comprises more memory devices than said second or third memory array.

7. The memory according to claim 6 , wherein said first memory array stores data.

8. The memory according to claim 7 , wherein said data include digital books, digital maps, digital music, digital movies, and/or digital videos.

9. The memory according to claim 6 , wherein said second or third memory array stores code.

10. The memory according to claim 9 , wherein said code includes operating system, software, and/or digital games.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2025
From: HANGZHOU HAICUN INFORMATION TECHNOLOGY CO., LTD.
To: SHENZHEN CUNTIAN TECHNOLOGY CO., LTD.
Reel/Frame 072727/0390 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2025
From: ZHANG, GUOBIAO, DR.
To: HANGZHOU HAICUN INFORMATION TECHNOLOGY CO., LTD.
Reel/Frame 070719/0038 →
Priority Claims (2)
CN 2017 1 0109704 · Feb 28, 2017 · national
CN 2017 1 0119051 · Mar 2, 2017 · national
Continuity (3)
Continuation In Part 14636353 · Mar 3, 2015
Provisional Application 61979504 · Apr 14, 2014
Related Publication 20170229158A1 · Aug 10, 2017