Lock-free raid implementation in multi-queue architecture
Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.
1. A method for lock-free RAID implementation, comprising:
receiving at a first core a client input/output (IO) request having a data address;
computing a stripe number as a function of the data address;
computing a central processing unit (CPU) core number as a function of the stripe number;
routing the request to a second core having the computed CPU core number;
updating a local data structure for the stripe number in a computer CPU cache on the second core;
and routing the request back to the first core.
2. The method of claim 1 , further comprising checking and updating a data cache in a local memory controller on the second core.
3. The method of claim 2 , further comprising updating data on drives consistently for the stripe number.
4. The method of claim 1 , further comprising completing the IO request.
5. The method of claim 1 , wherein neither the first core nor the second core have a lock on the stripe number.
6. A storage appliance, comprising:
a plurality of central processing unit (CPU) sockets, each socket including a plurality of cores,
wherein each core operates independently without locks, the storage appliance adapted to:
receive at a first core a client input/output (IO) request having a data address;
compute a stripe number as a function of the data address; computing a central processing unit (CPU) core number as a function of the stripe number;
route the request to a second core having the computed CPU core number;
update a local data structure for the stripe number in a computer CPU cache on the second core; and
route the request back to the first core.
7. The storage appliance of claim 6 , wherein the steps further comprise checking and updating data cache in a local memory controller on the second core.
8. The storage appliance of claim 7 , wherein the steps further comprise updating data on drives consistently for the stripe number.
9. The storage appliance of claim 6 , wherein the steps further comprise completing the IO request.
10. The storage appliance of claim 6 , wherein none of the plurality of cores has a lock on the stripe number.
11. A storage appliance, comprising:
a plurality of central processing unit (CPU) sockets, each socket including a plurality of cores;
wherein each core operates independently without locks;
wherein when acted upon by a processor, is adapted for performing the following steps:
receiving at a first core a client input/output (IO) request having a data address;
computing a stripe number as a function of the data address;
computing a central processing unit (CPU) core number as a function of the stripe number;
routing the request to a second core having the computed CPU core number;
updating a local data structure for the stripe number in a computer CPU cache on the second core; and
routing the request back to the first core, wherein none of the plurality of cores has a lock on the stripe.
12. The storage appliance of claim 11 , wherein the steps further comprise checking and updating a data cache in a local memory controller on the second core.
13. The storage appliance of claim 12 , wherein the steps further comprise updating data on drives consistently for the stripe number.