PCIe switch with data and control path systolic array
The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.
1. A method for Peripheral Component Interconnect Express (PCIe) switching, comprising:
receiving a transaction layer packet (TLP) at an uplink port of a PCIe switch;
at the PCIe switch:
determining a nature of the TLP by evaluating a parameter of the TLP at a programmable filter coupled to the uplink port;
determining if the TLP should be routed to a systolic array at the PCIe switch based on the nature of the TLP determined by the programmable filter;
routing the TLP to a systolic array at the PCIe switch based on a determination that the TLP should be routed to the systolic array at the PCIe switch;
analyzing, at the PCIe switch, the TLP in the systolic array; and
forwarding the TLP to a destination port of the PCIe switch based on the analysis of the TLP performed by the systolic array of the PCIe switch.
2. The method of claim 1 , wherein only a header portion of the TLP is routed to the systolic array.
3. The method of claim 1 , wherein the TLP routed to the systolic array is the TLP received at the uplink port.
4. The method of claim 1 , wherein the TLP routed to the systolic array is a replica of the TLP directly forwarded to the destination port.
5. The method of claim 1 , wherein the systolic array has an interface to communicate with a plurality of destination ports.
6. The method of claim 5 , wherein each of the destination ports has an associated filter.
7. A Peripheral Component Interconnect Express (PCIe) switch, comprising:
an uplink port for receiving a transaction layer packet (TLP) at the PCIe switch;
a programmable filter coupled to the uplink port, the programmable filter for determining a nature of the TLP received at the uplink port by evaluating a parameter of the received TLP, determining if the TLP should be routed to a systolic array at the PCIe switch based on the nature of the TLP determined by the programmable filter and routing the TLP to the systolic array at the PCIe switch based on a determination that the TLP should be routed to the systolic array at the PCIe switch;
the systolic array for analyzing the TLP at the PCIe switch and forwarding the TLP to a destination port of the PCIe switch based on the analysis of the TLP performed by the systolic array of the PCIe switch; and
a destination port for receiving the TLP.
8. The switch of claim 7 , wherein the systolic array only receives a header portion of the TLP.
9. The switch of claim 7 , wherein the systolic array receives the TLP as it was received by the uplink port.
10. The switch of claim 7 , wherein the programmable filter creates a replica of the TLP that it forwards to the destination port, and forwards the replica to the systolic array.
11. The switch of claim 7 , wherein the destination port comprises a plurality of downlink ports.
12. The switch of claim 7 , wherein the systolic array comprises an interface to communicate with a plurality of downlink ports.
13. The switch of claim 12 , wherein each of the downlink ports has an associated filter.
14. The switch of claim 7 , wherein the systolic array comprises a plurality of data processing units (DPUs).
15. A Peripheral Component Interconnect Express (PCIe) switch, comprising:
an uplink port for receiving a transaction layer packet (TLP) at the PCIe switch;
a first programmable filter coupled to the uplink port, the programmable filter for determining a nature of the TLP received at the uplink port by evaluating a parameter of the received TLP, determining if the TLP should be routed to a systolic array at the PCIe switch based on the nature of the TLP determined by the programmable filter and routing the TLP to the systolic array at the PCIe switch based on a determination that the TLP should be routed to the systolic array at the PCIe switch;
the systolic array for analyzing the TLP at the PCIe switch, determining a first destination port of a plurality of destination ports based on the analysis of the TLP performed by the systolic array of the PCIe switch and forwarding the TLP to the determined first destination port;
the plurality of destination ports for receiving the TLP; and
a plurality of second programmable filters associated with each of the plurality of second programmable filter associated with a respective one of the destination ports.
16. The switch of claim 15 , wherein the systolic array only receives a header portion of the TLP.
17. The switch of claim 15 , wherein the systolic array receives the TLP as it was received by the uplink port.
18. The switch of claim 15 , wherein the first programmable filter creates a replica of the TLP that it forwards to any of the destination ports, and forwards the replica to the systolic array.
19. The switch of claim 15 , wherein the systolic array comprises a plurality of data processing units (DPUs).