Under-channel gate transistors

1. A method for forming a transistor, comprising:

anisotropically etching a stacked semiconductor layer and dielectric layer to form a semiconductor fin from a first material on a dielectric fin;

etching away material from the dielectric layer directly underneath a channel region of the semiconductor fin, with the semiconductor fin still being supported by the dielectric layer in a source and drain region and with a continuous remnant of the dielectric layer remaining underneath the semiconductor fin;

forming a gate stack around the channel region of the semiconductor fin, with a portion of the gate stack underneath the semiconductor fin having a vertical thickness greater than a vertical thickness of a portion of the gate stack above the semiconductor fin.

2. The method of claim 1 , further comprising forming a dummy gate fin over the semiconductor fin, the dummy gate fin having a long dimension that is perpendicular to a long dimension of the semiconductor fin.

3. The method of claim 2 , further comprising forming dielectric sidewalls on the dummy gate fin.

4. The method of claim 3 , further comprising etching away the dummy gate fin after forming the dielectric sidewalls to expose the channel region of the semiconductor fin.

5. The method of claim 4 , wherein etching away material from the dielectric layer is performed after etching away the dummy gate.

6. The method of claim 3 , further comprising forming source and drain extensions on the source and drain region of the semiconductor after forming the dielectric sidewalls.

7. The method of claim 3 , wherein forming the gate stack comprises:

conformally depositing a work function layer on the semiconductor fin, the dielectric sidewalls, and the dielectric layer;

depositing a gate conductor on the work function layer; and

polishing the work function layer and the gate conductor down to a height of the dielectric sidewalls.

8. The method of claim 7 , further comprising:

recessing the gate stack below the height of the dielectric sidewalls; and

forming a dielectric gate cap over the gate stack to the height of the dielectric sidewalls.

9. The method of claim 1 , further comprising:

forming an inter-layer dielectric over the gate stack; and

forming respective contacts through the inter-layer dielectric to the gate stack and to the source and drain region of the semiconductor fin.

10. A method for forming a transistor, comprising:

anisotropically a stacked semiconductor layer and dielectric layer to form a semiconductor fin from a first material on a dielectric fin;

forming a dummy gate fin over the semiconductor fin, the dummy gate having a long dimension that is perpendicular to a long dimension of the semiconductor fin;

forming dielectric sidewalls on the dummy gate fin;

etching away the dummy gate fin after forming the dielectric sidewalls to expose the channel region of the semiconductor fin;

etching away material from the dielectric layer directly underneath a channel region of the semiconductor fin, with the semiconductor fin still being supported by the dielectric layer in a source and drain region and with a continuous remnant of the dielectric layer remaining underneath the semiconductor fin;

forming a gate stack around the channel region of the semiconductor fin, with a portion of the gate stack underneath the semiconductor fin having a vertical thickness greater than a vertical thickness of a portion of the gate stack above the semiconductor fin.

11. The method of claim 10 , wherein etching away material from the dielectric layer is performed after etching away the dummy gate.

12. The method of claim 10 , further comprising forming source and drain extensions on the source and drain region of the semiconductor after forming the dielectric sidewalls.

13. The method of claim 10 , wherein forming the gate stack comprises:

conformally depositing a work function layer on the semiconductor fin, the dielectric sidewalls, and the dielectric layer;

depositing a gate conductor on the work function layer; and

polishing the work function layer and the gate conductor down to a height of the dielectric sidewalls.

14. The method of claim 13 , further comprising:

recessing the gate stack below the height of the dielectric sidewalls; and

forming a dielectric gate cap over the gate stack to the height of the dielectric sidewalls.

15. A semiconductor device, comprising:

a dielectric layer;

a semiconductor fin supported directly by a dielectric layer in a source and drain region, wherein the dielectric layer forms a continuous layer underneath the semiconductor fin;

a gate stack comprising a gate dielectric and a gate conductor formed on a channel region of the semiconductor fin and on the dielectric layer, the gate stack being formed in contact with an entire circumference of the semiconductor fin, wherein a portion of the gate stack underneath the semiconductor fin has a vertical thickness greater than a vertical thickness of a portion of the gate stack above the semiconductor fin and wherein the gate stack is recessed below a height of sidewalls formed on the dielectric layer around the gate stack.

16. The semiconductor device of claim 15 , wherein the dielectric layer is recessed in an area between the sidewalls.

17. The semiconductor device of claim 15 , further comprising a dielectric gate cap on the gate stack having a top surface at a same height as the sidewalls.

18. The semiconductor device of claim 15 , wherein a portion of the gate stack is formed directly underneath the dielectric sidewalls.

19. The method of claim 1 , wherein no part of the gate stack penetrates the continuous remnant of the dielectric layer.

20. The semiconductor device of claim 15 , wherein no part of the gate stack penetrates the continuous dielectric layer underneath the semiconductor fin.