Semiconductor device having biasing structure for self-isolating buried layer and method therefor
A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.
1. A semiconductor device structure comprising:
a semiconductor substrate having first and second opposing major surfaces, wherein the semiconductor substrate includes:
a floating buried doped region of a first conductivity type;
a first doped region of a second conductivity type disposed between the floating buried doped region and the first major surface; and
a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;
a trench isolation structure extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein:
the floating buried doped region abuts the trench isolation structure; and
the trench isolation structure defines a perimeter for an active region of the semiconductor device structure;
an insulated trench structure extending from the first major surface through the first doped region and terminating within the floating buried doped region, wherein:
the insulated trench structure is disposed within the perimeter of the trench isolation structure;
the insulated trench structure defines a first portion and a second portion of the active region; and
the floating buried doped region electrically couples the first portion and the second portion of the active region together;
a first semiconductor device disposed within the first doped region and within the second portion of the active region;
a first conductive electrode electrically coupled to the first semiconductor device; and
a second conductive electrode electrically coupled to the first portion of the active region, wherein:
the second conductive electrode, the first portion of the active region, and the floating buried doped region form a bias semiconductor device configured to set a potential of the floating buried doped region.
2. The structure of claim 1 , wherein the first doped region and the semiconductor region are provided absent any diffused contact structures or conductive contact structures making direct or low-ohmic contact to the floating buried doped region.
3. The structure of claim 1 further comprising a second doped region of the first conductivity type disposed within the first doped region and within the first portion of the active region, wherein:
the second doped region is separated from the floating buried doped region by a portion of the first doped region; and
the second conductive electrode is connected to electrically short the second doped region and the first portion of the active region together.
4. The structure of claim 1 further comprising:
a second doped region of the first conductivity type disposed within the first doped region and within the first portion of the active region, wherein the second doped region is separated from the floating buried doped region by a portion of the first doped region; and
a third conductive electrode electrically coupled to the second doped region within the first portion of the active region.
5. The structure of claim 1 , wherein the floating buried doped region has a varying dopant concentration.
6. The structure of claim 5 , wherein the floating buried doped region comprises:
a first region adjoining the first doped region; and
a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region.
7. The structure of claim 6 , wherein the floating buried doped region further comprises a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.
8. The structure of claim 7 , wherein the insulated trench structure terminates within the third region of the floating buried doped region.
9. The structure of claim 7 , wherein the insulated trench structure terminates within the second region of the floating buried doped region.
10. The structure of claim 1 , wherein the bias semiconductor device comprises a diode.
11. A semiconductor device structure comprising:
a semiconductor substrate having first and second opposing major surfaces, wherein the semiconductor substrate comprises:
a floating buried doped region of a first conductivity type;
a first doped region of a second conductivity type disposed between the floating buried doped region and the first major surface; and
a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;
a pair of laterally separated trench isolation portions extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region;
an insulated trench structure laterally disposed between the pair of laterally separated trench isolation portions and extending from the first major surface and terminating within the floating buried doped region, wherein:
the insulated trench structure defines a first portion and a second portion of an active region; and
the first portion and the second portion are electrically coupled together through the floating buried doped region;
a semiconductor device disposed within the second portion of the active region and within the first doped region;
a first conductive electrode electrically coupled to the semiconductor device; and
a second conductive electrode electrically coupled to the first portion of the active region, wherein:
the second conductive electrode, the first portion of the active region, and the floating buried doped region form a bias semiconductor device; and
the bias semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the semiconductor device.
12. The structure of claim 11 , wherein the floating buried doped region comprises:
a first region adjoining the first doped region;
a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region; and
a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.
13. The structure of claim 12 , wherein the insulated trench structure terminates within the third region of the floating buried doped region.
14. The structure of claim 12 , wherein the insulated trench structure terminates within the second region of the floating buried doped region.
15. The structure of claim 11 further comprising:
a second doped region of the first conductivity type disposed within the first doped region and within the first portion of the active region, wherein:
the second doped region terminates within the first doped region and is spaced apart from the floating buried doped region and forms a portion of the bias semiconductor device.
16. A method of forming a semiconductor device comprising:
providing a semiconductor substrate having first and second opposing major surfaces, wherein the semiconductor substrate comprises:
a floating buried doped region of a first conductivity type;
a first doped region of a second conductivity type disposed between the floating buried doped region and the first major surface; and
a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;
forming a pair of laterally separated trench isolation portions extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region;
forming an insulated trench structure laterally disposed between the pair of laterally separated trench isolation portions and extending from the first major surface and terminating within the floating buried doped region, wherein:
the insulated trench structure defines a first portion and a second portion of an active region; and
the first portion and the second portion are electrically coupled together through the floating buried doped region;
providing a semiconductor device disposed within the second portion of the active region and within the first doped region;
forming a first conductive electrode electrically coupled to the semiconductor device; and
forming a second conductive electrode electrically coupled to the first portion of the active region, wherein:
the second conductive electrode, the first portion of the active region, and the floating buried doped region form a bias semiconductor device; and
the bias semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the semiconductor device.
17. The method of claim 16 , wherein forming the pair of laterally separated trench isolation portions and forming the insulated trench structure are done in a single formation step.
18. The method of claim 16 , wherein providing the semiconductor substrate comprises providing the floating buried doped region comprising:
a first region adjoining the first doped region;
a second region disposed between the first region and the semiconductor region, wherein the first region has a lower dopant concentration than the second region; and
a third region disposed between the second region and the semiconductor region, wherein the third region has a lower dopant concentration than the second region.
19. The method of claim 18 , wherein forming the insulated trench structure comprises terminating the insulated trench structure with the third region of the floating buried doped region.
20. The method of claim 18 , wherein forming the insulated trench structure comprises terminating the insulated trench structure within the second region of the floating buried doped region.