IP Library Patent Application 15502212
Patent Application
App. No. 15/502,212

Anti-Reflective Treatment Of The Rear Side Of A Semiconductor Wafer

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
15/502,212
Abstract

A method for producing a semiconductor wafer, in which an optical anti-reflective layer ( 4 ) is formed on the backside of the wafer in order to optimize optical access ( 17 ) to or from CMOS devices ( 10 ) through the backside ( 3 2 ) of the wafer ( 1 ). The CMOS devices ( 10 ) are produced only after formation of an anti-reflective layer ( 4 ), the etching stop layers ( 5, 6 ) formed thereon, the bonding layer ( 7 ) and the carrier wafer ( 8 ) bonded thereto. After formation of the CMOS devices, the etching stop layers ( 5, 6 ), the bonding layer ( 7 ) and the bonded carrier wafer ( 8 ) are thinned and removed, at least selectively, by grinding or by means of lithography ( 16 ) or masked etching.

Claims (27)

1 . A method for producing a semiconductor device, the method comprising the following steps:

a production step wherein a plurality of circuit components ( 10 ) are produced on a face ( 22 ) of a base wafer ( 1 ′) and the circuit components ( 10 ) comprise at least one photosensitive or photogenic optoelectronic component ( 10 );

a first anti-reflection step wherein at least one dielectric anti-reflective layer ( 4 , 5 ′) is created on a backside ( 31 ) of the base wafer ( 1 ′);

wherein the first anti-reflection step is performed prior to the production step.

2 . The method according to claim 1 , further comprising at least one coating step, in which at least one further layer ( 5 , 6 , 7 ) is created on or applied to the anti-reflective layer ( 4 ), wherein the at least one further layer comprises a second anti-reflective layer ( 5 ′) or at least one etching stop layer, and wherein the at least one coating step is performed subsequent to the anti-reflection step and prior to the production step.

3 . The method according to claim 2 , further comprising at least one first application of a first carrier wafer ( 8 ) to the backside ( 31 ) of the base wafer ( 1 ), wherein the first application of the first carrier wafer ( 8 ) is performed subsequent to the anti-reflection step and prior to the production step.

4 . The method according to claim 3 , wherein the at least one further layer ( 5 , 6 , 7 ) comprises a bonding layer ( 7 ), and wherein the application of the first carrier wafer ( 8 ) includes bonding the first carrier wafer ( 8 ) to the bonding layer ( 7 ).

5 . The method according to claim 4 , further comprising at least one thinning step performed subsequent to the production step, wherein a thickness of the applied first carrier wafer ( 8 ) is reduced.

6 . The method according to claim 5 , wherein the thinning step comprises a substantially uniform or complete removal of the first carrier wafer ( 8 ) from the backside ( 32 ) of the base wafer ( 1 ′).

7 . The method according to claim 1 , further comprising a second application of a second carrier wafer ( 18 ) to the face ( 23 ) of the base wafer ( 1 ′), wherein the second application is performed subsequent to the production step and prior to the thinning step.

8 . The method according to claim 7 , wherein the second carrier wafer ( 18 ) is removed, at least in part, subsequent to the thinning step.

9 . The method according to claim 1 , further comprising a selective removal of material of the at least one further layer ( 5 , 6 , 7 ) or of the thinned first carrier wafer ( 8 ) in at least one selected location ( 17 ) on the backside ( 32 ) of the base wafer ( 1 ′), wherein the at least one selected location ( 17 ) on the backside ( 32 ) is located opposite to the at least one optoelectronic component ( 10 ) formed on the face ( 22 ) of the base wafer.

10 . The method according to claim 9 , wherein the selective removal comprises a masked method or a lithographic method.

11 . The method according to claim 9 , wherein tapered light windows ( 16 ) are opened through the at least one further layer ( 5 , 6 , 7 ) or through the thinned first carrier wafer ( 8 ) up to the at least one selected location ( 17 ) of the anti-reflective layer ( 4 , 5 ′).

12 . The method according to claim 1 , wherein the production step includes a CMOS method, and the circuit components ( 10 ) comprise CMOS devices.

13 . The method according to claim 1 , wherein the anti-reflective layer ( 4 , 5 ′) includes an Si 3 N 4 layer having a thickness of 10 nm to 60 nm.

14 . The method according to claim 1 , wherein the second anti-reflective layer ( 4 , 5 ′) includes an oxide layer ( 5 ′) having a thickness of 1 nm to 5 nm.

15 . (canceled)

16 . A method of producing a semiconductor device, the method comprising the following steps:

providing a base wafer having a face side and a backside; and comprising

a first anti-reflection providing step comprising creating at least one dielectric anti-reflective layer on the backside of the base wafer; and

a production step comprising producing a plurality of circuit components on the face of the base wafer, wherein the circuit components comprise at least one photosensitive optoelectronic component.

17 . A method of producing a semiconductor device, the method comprising the following steps:

providing a base wafer having a face side and a backside;

and comprising

a first anti-reflection providing step comprising creating at least one dielectric anti-reflective layer on the backside of the base wafer;

a production step comprising producing a plurality of circuit components on the face of the base wafer, wherein the circuit components comprise at least one photogenic optoelectronic component.

Assignments (2)
CHANGE OF NAME Recorded Jul 23, 2019
From: X-FAB SEMICONDUCTOR FOUNDRIES AG
To: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
Reel/Frame 049841/0497 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2017
From: GAEBLER, DANIEL
To: X-FAB SEMICONDUCTOR FOUNDRIES AG
Reel/Frame 041789/0826 →