System and method for detecting voltage of battery pack
A system and method for detecting voltage of a battery pack. The system comprises a level transfer circuit array, a multipath data selector, a decoder, a trimming calibration circuit, and an output buffer. The decoder is configured to parse a battery pack cell gating signal; the level transfer circuit array is configured to convert a gated battery pack cell voltage into a common grounded voltage; the multipath data selector is configured to transmit the common grounded voltage, which is converted by the level transfer circuit array, of a battery pack cell to the trimming calibration circuit; the trimming calibration circuit is configured to correct the received common grounded voltage of the battery pack cell; and the output buffer is configured to buffer the common grounded voltage, which is trimmed and calibrated by the trimming calibration circuit, of the battery pack cell.
1. A battery pack voltage detection system, comprising a decoder, a level transfer circuit array, a multipath data selector, a trimming calibration circuit, an output buffer and a sampling unit;
the decoder is configured to parse a battery pack cell gating signal;
the level transfer circuit array is connected to the decoder, to convert a corresponding battery pack cell voltage into a common grounded voltage under control of the battery pack cell gating signal;
the multipath data selector is connected to the decoder and the level transfer circuit array, to transmit the common grounded voltage, which is converted by the level transfer circuit array, of a battery pack cell to the trimming calibration circuit according to the battery pack cell gating signal;
the trimming calibration circuit is connected to the decoder and the multipath data selector, to correct the received common grounded voltage of the battery pack cell; and
the output buffer is connected to the trimming calibration circuit, to buffer the common grounded voltage, which is trimmed and calibrated by the trimming calibration circuit, of the battery pack cell,
wherein the sampling unit comprises a sampling unit enable circuit, a high side bleeder circuit, a voltage-to-current circuit, and a voltage reduction circuit;
the sampling unit enable circuit comprises an enable generation circuit, a first current source, and a second current source; the enable generation circuit is separately connected to the first current source and the second current source, to enable the first current source and the second current source; the first current source is configured to provide current for the voltage-to-current circuit, and the second current source is configured to provide current for the high side bleeder circuit;
the high side bleeder circuit comprises a first voltage divider resistor string, a second voltage divider resistor string, and a mirror current source; after the first voltage divider resistor string, the second voltage divider resistor string, and the mirror current source are sequentially connected in series, two ends are separately connected to positive and negative input ends of the sampling unit;
the voltage-to-current circuit comprises an operational amplifier, a PMOS transistor, and a third resistor; a positive input end of the operational amplifier is connected to a point, where the first voltage divider resistor string is connected to the second voltage divider resistor string; a negative input end of the operational amplifier is connected to a drain of the PMOS transistor; an output end of the operational 1 amplifier is connected to a gate of the PMOS transistor; a source of the PMOS transistor 2 is connected to the voltage reduction circuit; one end of the third resistor is connected to the positive input end of the sampling unit, and the other end of the third resistor is connected to the drain of the PMOS transistor; and
the voltage reduction circuit comprises a fourth resistor, and one end of the fourth resistor is connected to the source of the PMOS transistor, and the other end of the fourth resistor is grounded.
2. The battery pack voltage detection system as in claim 1 , wherein the level transfer circuit array comprises an enable generation circuit and several sampling units; the enable generation circuit is configured to generate an enable signal, which corresponds to a sampling unit, of a gated channel according to the battery pack cell gating signal; the sampling unit is configured to convert a battery pack cell voltage of the gated channel into a common grounded voltage according to the enable signal, which corresponds to the sampling unit, of the gated channel.
3. The battery pack voltage detection system as in claim 2 , wherein positive and negative electrodes of the several sampling units are sequentially connected end to end, and the positive electrode and negative electrode of each battery pack cell are separately connected to positive and negative ends of a corresponding sampling unit.
4. The battery pack voltage detection system as in claim 1 , wherein the trimming calibration circuit comprises a programmable calibration code register and a programmable gain amplifier; the programmable calibration code register is configured to store a trimming and calibration code of each channel; and the programmable gain amplifier is configured to correct the common grounded voltage of the battery pack cell according to amplified gain corresponding to the trimming and calibration code corresponding to the battery pack cell gating signal.
5. A battery pack voltage detection method, comprising the following steps:
step S 1 , parsing, by a decoder, a battery pack cell gating signal;
step S 2 , generating, by a level transfer circuit array, an enable signal, which corresponds to a sampling unit, of a gated channel according to the battery pack cell gating signal, and under control of the signal, converting a floating-bias voltage of a battery pack cell of the gated channel into a common grounded voltage;
step S 3 , transmitting, by a multipath data selector, the converted common grounded voltage of the battery pack cell of the gated channel to a trimming calibration circuit according to a battery pack channel selection signal;
step S 4 , correcting, by the trimming calibration circuit, the received common grounded voltage of the battery pack cell; and
step S 5 , buffering, by an output buffer, the trimmed and calibrated common grounded voltage of the battery pack cell,
wherein the sampling unit comprises a sampling unit enable circuit, a high side bleeder circuit, a voltage-to-current circuit, and a voltage reduction circuit;
the sampling unit enable circuit comprises an enable generation circuit, a first current source, and a second current source; the enable generation circuit is separately connected to the first current source and the second current source, to enable the first current source and the second current source; the first current source is configured to provide current for the voltage-to-current circuit, and the second current source is configured for provide current to the high side bleeder circuit;
the high side bleeder circuit comprises a first voltage divider resistor string, a second voltage divider resistor string, and a mirror current source; after the first voltage divider resistor string, the second voltage divider resistor string, and the mirror current source are sequentially connected in series, two ends are separately connected to positive and negative input ends of the sampling unit;
the voltage-to-current circuit comprises an operational amplifier, a PMOS transistor, and a third resistor; a positive input end of the operational amplifier is connected to a point, where the first voltage divider resistor string is connected to the second voltage divider resistor string; a negative input end of the operational amplifier is connected to a drain of the PMOS transistor; an output end of the operational 1 amplifier is connected to a gate of the PMOS transistor: a source of the PMOS transistor 2 is connected to the voltage reduction circuit: one end of the third resistor is connected to the positive input end of the sampling unit, and the other end of the third resistor is connected to the drain of the PMOS transistor; and
the voltage reduction circuit comprises a fourth resistor, and one end of the fourth resistor is connected to the source of the PMOS transistor, and the other end of the fourth resistor is grounded.
6. The battery pack voltage detection method as in claim 5 , wherein
the battery pack cell gating signal comprises a gating signal of a channel cell voltage, a low power consumption module signal, and a high speed sampling mode signal.
7. The battery pack voltage detection method as in claim 5 , wherein
the level transfer circuit array comprises an enable generation circuit and several sampling units; the enable generation circuit is configured to generate an enable signal, which corresponds to a sampling unit, of a gated channel according to the battery pack cell gating signal; the sampling unit is configured to convert a battery pack cell voltage of the gated channel into a common grounded voltage according to the enable signal, which corresponds to the sampling unit, of the gated channel; and
the trimming calibration circuit comprises a programmable calibration code register and a programmable gain amplifier; the programmable calibration code register is configured to store a trimming and calibration code of each channel; and the programmable gain amplifier is configured to correct the common grounded voltage of the battery pack cell according to amplified gain corresponding to the trimming and calibration code corresponding to the battery pack cell gating signal.
8. The battery pack voltage detection method as in claim 5 , wherein the common grounded voltage V OUT , which is converted and obtained by the sampling unit, of the battery pack cell is:
V
OUT
=
V
bat
R
1214
×
R
1219
(
R
1214
+
R
1215
)
×
R
1218
Vbat is a voltage value provided by a battery pack: R 1214 , R 1215 , R 1218 , and R 1219 are respectively resistance values of the first voltage divider resistor string, the second voltage divider resistor string, the third resistor, and the fourth resistor.