Method of producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

1. A method of producing an optoelectronic semiconductor chip comprising in order:

A) creating a nucleation layer on a sapphire growth substrate,

B) applying a mask layer onto the nucleation layer and patterning the mask layer into a plurality of mask islands,

C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by the mask islands, the coalescence layer having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, which when seen in a top view form a lattice and have trapezoidal cross-sectional surfaces,

D) further growing the coalescence layer predominantly with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer,

E) growing a multiple quantum well structure on the coalescence layer,

F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for reflection of some radiation generated in the multiple quantum well structure, and

G) detaching the growth substrate and the nucleation layer, and creating a roughening by etching the coalescence layer, wherein the mask layer serves as an etching mask,

wherein the mirror islands comprises a transparent, dielectric material, and

wherein the roughening remains in the optoelectronic semiconductor chip.

2. The method according to claim 1 , wherein

the nucleation layer comprises or consists of one or more partial layers of aluminum nitride, aluminum oxynitride and/or AlGaN,

the mask layer is made of a silicon oxide and/or a silicon nitride,

the coalescence layer is made of GaN or of GaN and AlGaN,

the multiple quantum well structure is based on the material system AlInGaN and generates blue light, and

before step F), a top layer is fixated between the mirror and the multiple quantum well structure, which is made of p-doped GaN and, in some areas, extends into recesses of the multiple quantum well structure.

3. The method according to claim 2 , wherein

the contact regions comprise or consist of Ag, Al and/or ZnO and the contact regions directly between the mirror islands are in direct contact with the top layer,

the top layer is applied directly onto the multiple quantum well structure,

the mirror islands are in direct contact with the top layer and are electrically insulating, and

the mirror islands are covered on a side facing away from the multiple quantum well structure by a closing mirror layer disposed on the mirror islands composed of a same material of the contact regions.

4. The method according to claim 2 , wherein, in a region of the mirror island, in a direction away from the top layer, the mirror consists of partial layers in the specified order:

100 nm to 500 nm SiO 2 ,

1 nm to 20 nm ZnO,

50 nm to 300 nm Ag, and

2 nm to 150 nm ZnO.

5. The method according to claim 1 , wherein the lattice composed of upper sides of the ribs facing away from the growth substrate and the metallic contact regions directly between the mirror islands have a regular hexagonal structure, seen in a top view.

6. The method according to claim 1 , wherein the mask islands seen in a top view are circular and arranged in a regular hexagonal shape, an average diameter of the mask islands is 0.5 μm to 3 μm, and an average distance between adjacent mask islands is 0.5 μm to 3 μm.

7. The method according to claim 1 ,

wherein, before step G), a carrier is applied on the mirror, and

current is applied to the multiple quantum well structure with electrical connections.

8. The method according to claim 1 ,

wherein, on a side of the coalescence layer facing away from the growth substrate, a higher dislocation density is present over the ribs than between the ribs, and

the multiple quantum well structure has a higher density of V-defects over the ribs than between the ribs.

9. The method according to claim 8 , wherein regions with a higher density of V-defects, starting from the metallic contact regions, conduct current into the multiple quantum well structure in a direction perpendicular to the mirror.

10. The method according to claim 8 ,

wherein the roughening does not extend into the multiple quantum well structure, and

the V-defects extend from the mirror through the multiple quantum well structure towards the coalescence layer.

11. The method according to claim 1 ,

wherein the mask islands or a portion of the mask islands comprise/comprises silicon nitride and have/has an absorptance of at least 60% for at least a portion of the spectrum between 240 nm and 480 nm.

12. An optoelectronic semiconductor chip produced by the method according to claim 11 .

13. A method of producing an optoelectronic semiconductor chip comprising in order:

A) creating a nucleation layer on a sapphire growth substrate,

B) applying a mask layer onto the nucleation layer and patterning the mask layer into a plurality of mask islands,

C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by the mask islands, the coalescence layer having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, which when seen in a top view form a lattice and which have trapezoidal cross-sectional surfaces,

D) further growing the coalescence layer predominantly with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer,

E) growing a multiple quantum well structure on the coalescence layer,

F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for reflection of some radiation generated in the multiple quantum well structure, and

G) detaching the growth substrate and the nucleation layer, and creating a roughening by etching the coalescence layer, wherein the mask layer serves as an etching mask, and

wherein the roughening remains in the optoelectronic semiconductor chip.