Compound semiconductor device structures comprising polycrystalline CVD diamond
A semiconductor device structure comprising: a layer of compound semiconductor material; and a layer of polycrystalline CVD diamond material, wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBR eff ) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m 2 K/GW.
1. A semiconductor device structure comprising:
a layer of compound semiconductor material; and
a layer of polycrystalline CVD diamond material,
wherein the layer of polycrystalline CVD diamond material is bonded to the layer of compound semiconductor material via a layer of nano-crystalline diamond which is directly bonded to the layer of compound semiconductor material, the layer of nano-crystalline diamond having a thickness in a range 5 to 50 nm and configured such that an effective thermal boundary resistance (TBR eff ) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 50 m 2 K/GW.
2. A semiconductor device structure according to claim 1 , wherein the thickness of the layer of nano-crystalline diamond is in a range 10 to 40 nm.
3. A semiconductor device structure according to claim 1 , wherein the thickness of the layer of nano-crystalline diamond is in a range 15 to 30 nm.
4. A semiconductor device structure according to claim 1 , wherein the layer of nano-crystalline diamond has a volume fraction of voids as measured using transmission electron microscopy imaging of no more than 10%.
5. A semiconductor device structure according to claim 4 , wherein the volume fraction of voids in the layer of nano-crystalline diamond is no more than 8%.
6. A semiconductor device structure according to claim 1 , wherein the layer of nano-crystalline diamond has no voids having a thickness greater than 20 nm in a representative sample comprising an area of at least 200 nm×100 nm.
7. A semiconductor device structure according to claim 6 , wherein the layer of nano-crystalline diamond comprises no voids having a thickness greater than 15 nm in a representative sample comprising an area of at least 200 nm×100 nm.
8. A semiconductor device structure according to claim 1 , wherein the layer of nano-crystalline diamond has no visible voids discernible in transmission electron microscopy imaging in a representative sample comprising an area of at least 200 nm×100 nm.
9. A semiconductor device structure according to claim 1 , wherein the layer of polycrystalline CVD diamond material has a thickness of at least 5 micrometers.
10. A semiconductor device structure according to claim 1 , wherein the layer of polycrystalline CVD diamond material comprises grains having a size greater than 1 micron.
11. A semiconductor device structure according to claim 1 , wherein the effective thermal boundary resistance (TBR eff ) as measured by transient thermoreflectance at an interface between the layer of compound semiconductor material and the layer of polycrystalline CVD diamond material is no more than 40 m 2 K/GW.
12. A semiconductor device structure according to claim 1 , wherein the layer of compound semiconductor material comprises a III-V compound semiconductor material.
13. A semiconductor device structure according to claim 12 , wherein the III-V compound semiconductor material is gallium nitride.
14. A semiconductor device structure according to claim 1 , wherein the compound semiconductor layer has one or more of the following characteristics:
a charge mobility of at least 1200 cm 2 V −1 s −1 ;
a sheet resistance of no more than 700 Ω/square;
a current leakage of no more than 10 −5 amps; and
a maximum power of at least 5 W/mm.
15. A semiconductor device structure comprising:
a GaN layer;
a dielectric layer disposed on the GaN layer;
a layer of nano-crystalline diamond disposed on the dielectric layer; and
a layer of polycrystalline CVD diamond material disposed on the layer of nano-crystalline diamond,
wherein the dielectric layer has a thickness in a range 28-100 nm and an effective thermal boundary resistance (TBR eff ) as measured by transient thermoreflectance at an interface between the GaN layer and the layer of polycrystalline CVD diamond material is 12-50 m 2 K/GW, and
wherein the layer of nano-crystalline diamond has no voids having a thickness greater than 20 nm in a representative sample comprising an area of at least 200 nm×100 nm.
16. A semiconductor device structure according to claim 15 , wherein the dielectric layer comprises a ceramic material.
17. A semiconductor device structure according to claim 15 , further comprising:
an AlGaN layer, the GaN layer being disposed on the AlGaN layer.
18. A semiconductor device structure according to claim 15 , wherein the layer of nano-crystalline diamond has a volume fraction of voids of no more than 10%.