IP Library › Granted Patent US 10,461,698
Granted Patent B2
US 10,461,698 · App. 15/547,167 · Granted Oct 29, 2019

Signal processing apparatus and method

Inventor: Tomohiro Matsumoto (Kanagawa, JP)
Assignee: Sony Corporation
H03D7/168H03D7/1441H03D7/1466H03D7/1483H03D7/165H03K3/017H03K5/15093H03K21/023H04B1/123H04B1/26H03D2200/0084H03D2200/0086H04B1/12
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Quick Facts
Patent No.
US 10,461,698
App. No.
15/547,167
Granted
Oct 29, 2019
Kind
B2
Abstract

The present technology relates to a signal processing apparatus and method capable of increasing a harmonic rejection ratio while suppressing an increase in power consumption. In one aspect of the present technology, two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period are mixed with each signal of a differential signal, and a difference between results of the mixing of the two local signals is calculated. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer that controls those apparatuses.

Claims (48)

1. A signal processing apparatus comprising:

a mixing section that has a differential configuration, mixes two local signals with each signal of a differential signal, and calculates a difference between results of the mixing of the two local signals, the two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period; and

a resonance section that resonates with the differential signal, with which the local signals are mixed by the mixing section, at a predetermined resonant frequency.

2. The signal processing apparatus according to claim 1 , wherein

the resonance section resonates at a sixfold frequency of a frequency of the local signals.

3. The signal processing apparatus according to claim 1 , wherein

the resonance section includes a parallel LC circuit.

4. The signal processing apparatus according to claim 1 , wherein

the resonant frequency is variable.

5. The signal processing apparatus according to claim 1 , further comprising

a voltage/current conversion section that converts a voltage into a current with respect to the differential signal, wherein

the mixing section mixes the local signals with the differential signal output from the voltage/current conversion section.

6. The signal processing apparatus according to claim 5 , further comprising

a capacitor between an output of the voltage/current conversion section and a ground potential.

7. The signal processing apparatus according to claim 1 , further comprising

a differential amplification section that amplifies the differential signal, with which the local signals are mixed by the mixing section.

8. The signal processing apparatus according to claim 1 , wherein

the mixing section includes a path of an I channel and a path of a Q channel, mixes a first set of two local signals with each signal of the I channel of the differential signal, and mixes a second set of two local signals with each signal of the Q channel of the differential signal, corresponding local signals of the first set and the second set having a mutual phase difference of 90 degrees.

9. The signal processing apparatus according to claim 1 , further comprising

a local signal generation section that generates the local signals, wherein

the mixing section mixes the local signals with the differential signal, the local signals being generated by the local signal generation section.

10. A signal processing method, comprising:

mixing two local signals with each signal of a differential signal and calculating a difference between results of the mixing of the two local signals, the two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period; and

resonating with the differential signal, with which the local signals are mixed, at a predetermined resonant frequency.

11. The A signal processing apparatus comprising:

a generation section that generates two local signals to be mixed with a differential signal, the two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period, wherein

the generation section includes

a plurality of flip-flops mutually connected in series in a ring form, and

a computing section that calculates a logical OR of an input and an output of each of the flip-flops.

12. The signal processing apparatus according to claim 11 , wherein

the generation section causes each of the flip-flops to sequentially hold a value “1” according to an input clock signal.

13. The signal processing apparatus according to claim 11 , wherein

a frequency of the clock signal is a sixfold frequency of a frequency of the local signals, and

the generation section has a ring configuration constituted of the six flip-flops and the six computing sections and outputs the two local signals that are outputs of the two computing sections separated from each other with other two computing sections therebetween.

14. The signal processing apparatus according to claim 13 , wherein

the generation section includes two sets of the ring configuration, and generates a first set of two local signals for an I channel by one of the sets of the ring configuration and a second set of two local signals for a Q channel by the other one of the sets of the ring configuration, corresponding local signals of the first set and the second set having a phase difference of 90 degrees.

15. The signal processing apparatus according to claim 11 , wherein

the generation section includes a frequency divider section that generates the local signals having a 1/3 frequency and a 1/3 duty ratio with respect to a clock signal having a threefold frequency of a frequency of the local signals.

16. The signal processing apparatus according to claim 15 , wherein

the frequency divider section includes

a counter that counts the clock signal,

a reset control section that resets the counter to “0” when an output value of the counter reaches “3”, and

an output control section that outputs a value “1” when a value of the counter is “2”, and outputs a value “0” when the output value of the counter is “1” or “0”.

17. The signal processing apparatus according to claim 11 , further comprising

a mixing section that mixes the local signals generated by the generation section with each signal of the differential signal.

18. A signal processing method, comprising:

generating two local signals to be mixed with a differential signal, the two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period by a plurality of flip-flops mutually connected in series in a ring form; and

calculating a logical OR of an input and an output of each of the flip-flops.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2017
From: MATSUMOTO, TOMOHIRO
To: SONY CORPORATION
Reel/Frame 043431/0041 →
Priority Claims (1)
JP 2015-021075 · Feb 5, 2015 · national
Continuity (1)
Related Publication 20180019707A1 · Jan 18, 2018
Cited By (1)
US 12,494,156