IP Library › Granted Patent US 10,754,991
Granted Patent B2
US 10,754,991 · App. 15/549,712 · Granted Aug 25, 2020

Method to isolate real-time or safety-critical software and operating system from non-critical software and operating system

Inventor: Konrad Schwarz (Neubiberg, DE)
Assignee: SIEMENS AKTIENGESELLSCHAFT
G06F21/74G06F21/50G06F21/71
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Quick Facts
Patent No.
US 10,754,991
App. No.
15/549,712
Granted
Aug 25, 2020
Kind
B2
Abstract

A method is provided to isolate a secure operation region with a safety-critical software and real-time operating system from a non-secure operation region with non-critical software and general operating system including a non-secure mode, wherein the real-time operating system is inactivated and the general operating system is activated by a secure configuration register and wherein secure interrupts are mapped to fast processor interrupts calling a secure monitor program and non-secure interrupts are mapped to regular processor interrupts by a interface configuration register, and further including a secure mode, wherein the real-time operating system is activated and the general operating system is inactivated by the secure configuration register and wherein secure interrupts are mapped to regular processor interrupts calling the real-time operating system, fast processor interrupts are not used and non-secure interrupts are disabled by the interface configuration register.

Claims (34)

1. A method to isolate a secure operation region with a safety-critical software and a real-time operating system from a non-secure operation region with a non-critical software and a general operating system, and synchronize interrupt services between the real-time operating system and the general operating system, comprising:

providing a non-secure mode:

wherein the real-time operating system is inactivated and the general operating system is activated by a secure configuration register, and

wherein secure interrupts are mapped to fast processor interrupts calling a secure monitor program and non-secure interrupts are mapped to regular processor interrupts by an interface configuration register; and

providing a secure mode:

wherein the real-time operating system is activated and the general operating system is inactivated by the secure configuration register, and

wherein secure interrupts are mapped to regular processor interrupts calling the real-time operating system, fast processor interrupts are not used and non-secure interrupts are disabled by the interface configuration register for the duration of operation in the secure mode.

2. The method according to claim 1 , further comprising:

providing a secure interrupt from a normal operation of the general operating system by initiating an interrupt service routine processing of the real-time operating system via a secure monitor program;

providing a secure monitor call from a normal operation of the general operating system by initiating a normal operation f the real-time operating system via the secure monitor program; and

providing a continuation call for the general operating system from a normal operation of the real-time operating system by initiating a normal operation of the general operating system via the secure monitor program.

3. The method according to claim 2 , wherein the secure monitor program is:

swapping non-secure/secure registers;

disabling non-secure interrupts and routing secure interrupts to regular processor interrupts by writing an interface configuration register if the general operating system is active;

enabling non-secure interrupts and routing secure interrupts to fast processor interrupts by writing the interface configuration register if the real-time operating system is active;

activating the real-time operating system by writing a secure configuration register if the general operating system is active;

activating the general operating system by writing a secure configuration register if the real-time operating system is active; and

terminating the secure monitor program.

4. A computer program product, comprising a computer readable hardware storage device having computer readable program code stored therein, said program code executable by a processor of a computer system to implement a method for isolating a secure operation region with a safety-critical software and a real-time operating system from a non-secure operation region with a non-critical software and a general operating system, and synchronizing interrupt services, comprising:

providing a non-secure mode:

wherein the real-time operating system is inactivated and the general operating system is activated by a secure configuration register, and

wherein secure interrupts are mapped to fast processor interrupts calling a secure monitor program and non-secure interrupts are mapped to regular processor interrupts by an interface configuration register; and

providing a secure mode:

wherein the real-time operating system is activated and the general operating system is inactivated by the secure configuration register, and

wherein secure interrupts are mapped to regular processor interrupts calling the real-time operating system, fast processor interrupts are not used and non-secure interrupts are disabled by the interface configuration register and cannot be enabled until the non-secure mode is used.

5. A computing system, comprising:

a processor;

a memory coupled to the processor;

a secure operation region with a safety-critical software and a real-time operating system; and

a non-secure operation region with a non-critical software and a general operating system;

wherein the real-time operating system and the general operating system are executed on the processor,

wherein the computing system is configured to isolate the secure operation region from the non-secure operation region, and synchronize interrupt services between the secure operation region and the non-secure operation region, by:

providing a non-secure mode wherein the real-time operating system is inactivated and the general operating system is activated by a secure configuration register and wherein secure interrupts are mapped to fast processor interrupts calling a secure monitor program and non-secure interrupts are mapped to regular processor interrupts by an interface configuration register; and

providing a secure mode wherein the real-time operating system is activated and the general operating system is inactivated by the secure configuration register and wherein secure interrupts are mapped to regular processor interrupts calling the real-time operating system, fast processor interrupts are not used and non-secure interrupts are disabled by the interface configuration register such that non-secure interrupts are only enabled in the non-secure mode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2017
From: SCHWARZ, KONRAD
To: SIEMENS AKTIENGESELLSCHAFT
Reel/Frame 043711/0989 →
Priority Claims (1)
DE 10 2015 202 438 · Feb 11, 2015 · national
Continuity (1)
Related Publication 20180068134A1 · Mar 8, 2018