SiC epitaxial wafer and method for manufacturing SiC epitaxial wafer

1. A SiC epitaxial wafer comprising a SiC epitaxial layer formed on a SiC single crystal substrate having an offset angle of 4 degrees or less in a<11-20>direction from a (0001) plane,

wherein a trapezoidal defect included in the SiC epitaxial wafer comprises an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow,

wherein the trapezoidal defect is on the surface of the epitaxial layer and the upper base of the trapezoidal defect is a lined shape.

2. The SiC epitaxial wafer according to claim 1 , wherein a ratio of the inverted trapezoidal defect in the trapezoidal defect is 50% or more.

3. The SiC epitaxial wafer according to claim 1 , wherein the length of the lower base on the downstream side of the step flow of the inverted trapezoidal defect is 0 and the inverted trapezoidal defect becomes a triangular shape.

4. A SiC epitaxial wafer comprising a SiC epitaxial layer formed on a SiC single crystal substrate having an offset angle of 4 degrees or less in a<11-20>direction from a (0001) plane,

wherein a trapezoidal defect included in the SiC epitaxial wafer comprises an inverted trapezoidal defect in which a length of a lower base on a downstream side of a step flow is equal to or less than a length of an upper base on an upstream side of the step flow,

wherein the trapezoidal defect is on the surface of the epitaxial layer and the upper base of the trapezoidal defect is a lined shape, and

wherein a ratio of the inverted trapezoidal defect in the trapezoidal defect is 75% or more.