IP Library › Granted Patent US 10,529,872
Granted Patent B2
US 10,529,872 · App. 15/559,081 · Granted Jan 7, 2020

Silicon-containing semiconductor structures, methods of making the same and devices including the same

Inventors: Horia M. Faur (Medina, OH); Maria Faur (North Olmsted, OH)
Assignee: SPECMAT, Inc.
H01L31/02168H01L31/028H01L31/02167H01L31/1804H01L31/1868H01L31/206H01L21/0203H01L21/30604Y02E10/50
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Quick Facts
Patent No.
US 10,529,872
App. No.
15/559,081
Granted
Jan 7, 2020
Kind
B2
Abstract

A semiconductor system includes a silicon substrate and a porous silicon region disposed on the silicon substrate. The porous silicon region is configured to passivate the surface of the silicon substrate via a field effect and to reduce reflection loss on the silicon substrate via an appropriate refractive index. The porous silicon region is manufactured by a stain etching process, which retrofits existing tools for junction isolation and Phosphorus Silicon Glass (PSG) etch in solar cell manufacturing. The retrofitted tools for junction isolation and PSG etch achieves multiple purposes in a single step, including etch-back, PSG etch, antireflection coating, and passivation of the front surface of the solar cell.

Claims (19)

1. A method of facilitating fabrication of a solar cell via a stain etching process using a junction isolation/phosphosilicate glass (PSG) etch processing tool, the method comprising:

(A) placing a first stain etching solution in a first reservoir coupled to a PSG etch tank in the junction isolation/PSG etch processing tool through a first chemical dosing unit of the PSG etch processing tool;

(B) placing at least a portion of a silicon substrate for the solar cell in the PSG etch tank and allowing contact, in the PSG etch tank, between the silicon substrate and the first stain etching solution in the first reservoir;

(C) removing possible PSG on a front side of the silicon substrate during a first time period via the contact between the silicon substrate and the first stain etching solution;

(D) etching back at least a portion of the front side of the silicon substrate during a second time period via the contact between the silicon substrate and the first stain etching solution; and

(E) passivating the front side of the silicon substrate and reducing a reflection loss on the front side of the silicon substrate, at least partially, by creating a front side porous silicon region on the front side of the silicon substrate during a third time period via the contact between the silicon substrate and the first stain etching solution,

wherein at least a portion of the second time period and the third time period is concurrent.

2. The method of claim 1 , wherein at least a portion of the first time period, the second time period, and the third time period is concurrent.

3. The method of claim 1 , further comprising:

(F) placing a second stain etching solution in a second reservoir coupled to a junction isolation process tank through a second chemical dosing unit of the junction isolation/PSG etch processing tool;

(G) placing at least a portion of the silicon substrate for the solar cell in the junction isolation process tank and allowing contact, in the junction isolation process tank, between the silicon substrate and the second stain etching solution in the second reservoir; and

(H) creating a back side porous silicon region on a back side of the silicon substrate via the contact between the silicon substrate and the second stain etching solution so as to passivate the back side of the silicon substrate.

4. The method of claim 3 , further comprising:

(I) doping the back side of the silicon substrate with a first doping material, before creating the back side porous silicon region.

5. The method of claim 4 , wherein Step (I) comprises at least one of a thermal diffusion process, an ion implantation process or a laser doping process.

6. The method of claim 4 , further comprising:

(J) doping the front side of the silicon substrate with a second doping material, before creating the front side porous silicon region.

7. The method of claim 4 , further comprising:

(K) depositing a silicon nitride (SiN x ) layer over the front side porous silicon layer via a plasma enhanced chemical vapor deposition (PECVD) process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2024
From: FAUR, HORIA M.; FAUR, MARIA
To: SPECMAT, INC.
Reel/Frame 068223/0542 →
Continuity (2)
Provisional Application 62135406 · Mar 19, 2015
Related Publication 20180076341A1 · Mar 15, 2018