Solid-state imaging device and electronic device with symmetrical transistor groups
The present disclosure relates to a solid-state imaging device and an electronic device for suppressing deterioration of pixel characteristics while guaranteeing the operating range of VSLs. A solid-state imaging device according to a first aspect of this disclosure has multiple pixel sharing units each including multiple photoelectric conversion sections each configured to correspond to a pixel, an accumulation section configured to be shared by the plurality of photoelectric conversion sections and to accumulate charges generated thereby, and multiple transistors configured to control reading of the charges accumulated in the accumulation section. The plurality of transistors in each pixel sharing unit are arranged symmetrically. The plurality of transistors include a transistor that functions as a switch to change conversion efficiency. The present disclosure may be applied to back-illuminated CMOS image sensors, for example.
1. A solid state imaging device comprising a plurality of pixel sharing units each including:
a first light receiving section including a plurality of photoelectric conversion sections that are each configured to correspond to a pixel;
a second light receiving section including a plurality of photoelectric conversion sections that are each configured to correspond to a pixel;
an accumulation section configured to be shared by the plurality of photoelectric conversion sections and to accumulate charges generated thereby; and
a plurality of transistors configured to control reading of the charges accumulated in the accumulation section and disposed in first and second transistor groups,
wherein the first transistor group is disposed adjacent a first side of the first light receiving section and between the first light receiving section and the second light receiving section,
wherein the second transistor group is disposed adjacent a first side of the second light receiving section,
wherein the plurality of transistors in each of the first and second transistor groups are arranged symmetrically,
and
wherein the second transistor group includes a transistor that functions as a switch to change conversion efficiency.
2. The solid-state imaging device according to claim 1 , wherein the transistor that functions as the switch is configured to change the conversion efficiency by selectively enabling or disabling additional capacitance with respect to the accumulation section.
3. The solid-state imaging device according to claim 2 , wherein the additional capacitance is configured to include the capacitance of the transistor that functions as the switch and diffusion capacitance.
4. The solid-state imaging device according to claim 3 , wherein the additional capacitance is configured to include wiring capacitance.
5. The solid-state imaging device according to claim 2 , wherein each of the pixel sharing units is configured to include a plurality of the accumulation sections.
6. The solid-state imaging device according to claim 2 , wherein each of the pixel sharing units is configured to include
eight of the photoelectric conversion sections each configured to correspond to a pixel, and
two of the accumulation sections configured to be shared by four of the photoelectric conversion sections.
7. The solid-state imaging device according to claim 2 , wherein each of the pixel sharing units is configured to include accumulation section wiring configured to connect a plurality of the accumulation sections, and
the accumulation section wiring is configured to be surrounded by a hollow region.
8. The solid-state imaging device according to claim 2 , wherein at least part of device isolation is accomplished using an oxide film.
9. The solid-state imaging device according to claim 2 , wherein device isolation is accomplished using ion implantation.
10. An electronic device comprising a solid-state imaging device having a plurality of pixel sharing units each configured to include:
a first light receiving section including a plurality of photoelectric conversion sections that are each configured to correspond to a pixel;
a second light receiving section including a plurality of photoelectric conversion sections that are each configured to correspond to a pixel;
an accumulation section configured to be shared by the plurality of photoelectric conversion sections and to accumulate charges generated thereby; and
a plurality of transistors configured to control reading of the charges accumulated in the accumulation section and disposed in first and second transistor groups,
wherein the first transistor group is disposed adjacent a first side of the first light receiving section and between the first light receiving section and the second light receiving section,
wherein the second transistor group is disposed adjacent a first side of the second light receiving section,
wherein the plurality of transistors in each of the first and second transistor groups are arranged symmetrically, and
wherein the second transistor group includes a transistor that functions as a switch to change conversion efficiency.
11. The solid-state imaging device according to claim 1 , wherein the plurality of transistors in the first and second transistor groups are symmetrical in that they form a symmetrical layout in which a source/drain region, a pixel transistor, a source/drain region, a pixel transistor, and a source drain region are disposed in that order.
12. The solid-state imaging device according to claim 1 , wherein each of the light receiving sections includes four photoelectric conversion sections.
13. The electronic device according to claim 10 , wherein the transistor that functions as the switch is configured to change the conversion efficiency by selectively enabling or disabling additional capacitance with respect to the accumulation section.
14. The electronic device according to claim 13 , wherein the additional capacitance is configured to include the capacitance of the transistor that functions as the switch and diffusion capacitance.
15. The electronic device according to claim 14 , wherein the additional capacitance is configured to include wiring capacitance.
16. The electronic device according to claim 13 , wherein each of the pixel sharing units is configured to include a plurality of the accumulation sections.
17. The electronic device according to claim 13 , wherein each of the pixel sharing units is configured to include
eight of the photoelectric conversion sections each configured to correspond to a pixel, and
two of the accumulation sections configured to be shared by four of the photoelectric conversion sections.
18. The electronic device according to claim 13 , wherein each of the pixel sharing units is configured to include accumulation section wiring configured to connect a plurality of the accumulation sections, and
the accumulation section wiring is configured to be surrounded by a hollow region.
19. The electronic device according to claim 13 , wherein at least part of device isolation is accomplished using an oxide film.
20. The electronic device according to claim 13 , wherein device isolation is accomplished using ion implantion.