Monolithically integrated photodetector and receiver
An example device in accordance with an aspect of the present disclosure includes an avalanche photodetector to enable carrier multiplication for increased responsivity, and a receiver based on source-synchronous CMOS and including adaptive equalization. The photodetector and receiver are monolithically integrated on a single chip.
1. A device comprising:
an avalanche photodetector to enable carrier multiplication for increased responsivity; and
a receiver including a transimpedance amplifier (TIA), an adaptively-tuned continuous-time linear equalizer (CTLE) cascaded with the TIA, and a slicer bank coupled to the CTLE to identify a data pass bit error rate (BER), wherein the receiver is based on source-synchronous complementary metal-oxide semiconductor (CMOS);
wherein the photodetector and receiver are monolithically integrated on a single chip.
2. The device of claim 1 , wherein the avalanche photodetector is a lateral junction avalanche photodetector including a plurality of P regions and a plurality of N regions implanted in a substrate as interdigitized spatially spaced fingers having intrinsic spacing therebetween.
3. The device of claim 2 , further comprising a well disposed in the substrate, wherein the plurality of P and N regions are embedded in the well, and the well is depletable by application of a bias to take away photo generated carriers outside the well.
4. The device of claim 3 , further comprising guard rings disposed on a periphery of the well to apply the bias to drain slower carriers to the substrate and enable faster carriers to transfer to at least one of the P and N regions.
5. The device of claim 2 , wherein the intrinsic spacing between the interdigitized spatially spaced fingers is on the order of approximately 40-60 nanometers (nm).
6. The device of claim 1 , wherein the receiver includes adaptive equalization.
7. The device of claim 1 , wherein the slicer bank includes at least one data slicer associated with a data pass bit error rate (BER), and at least one eye monitor slicer to sense a monitor slicer BER.
8. A device comprising:
a lateral junction avalanche photodetector including a plurality of P regions and a plurality of N regions implanted in a substrate as interdigitized spatially spaced fingers having intrinsic spacing therebetween, to enable carrier multiplication for increased responsivity; and
a receiver based on source-synchronous CMOS and including adaptive equalization;
wherein the photodetector and receiver are monolithically integrated on a single chip.
9. The device of claim 8 , wherein the receiver further comprises a transimpedance amplifier (TIA) including a large input-stage feedback resistor.
10. The device of claim 8 , wherein the receiver further comprises an adaptively-tuned continuous-time linear equalizer (CTLE) cascaded with the TIA to compensate for parasitic capacitance of the photodetector, wherein the CTLE includes the capability of being selectively enabled and disabled according to desired bandwidth and gain characteristics for the receiver.
11. The device of claim 10 , wherein the receiver further comprises an equalization control loop to adapt the CTLE peaking to accommodate variations in input capacitance associated with given photodetectors.
12. The device of claim 8 , wherein the receiver is clocked to synchronize data channels with a clock based on at least one of i) an on-chip clock source, and ii) an external clock.
13. The device of claim 8 , wherein the receiver further comprises a slicer bank including a plurality of data slicers associated with a data pass bit error rate (BER), and at least one eye monitor slicer to sense a monitor slicer BER.
14. The device of claim 13 , wherein the eye monitor slicer is provided with an offset corresponding to an increased voltage sweep relative to the data slicers.
15. A device comprising:
a lateral junction avalanche photodetector including a plurality of P regions and a plurality of N regions implanted in a substrate as interdigitized spatially spaced fingers having intrinsic spacing therebetween, to enable carrier multiplication for increased responsivity; and
a receiver including a transimpedance amplifier (TIA), an adaptively-tuned continuous-time linear equalizer (CTLE) cascaded with the TIA, and a slicer bank coupled to the CTLE to identify a data pass bit error rate (BER), wherein the receiver is based on source-synchronous complementary metal-oxide semiconductor (CMOS);
wherein the photodetector and receiver are monolithically integrated on a single chip.