Array substrate and display panel, and fabrication methods thereof

1. An array substrate, comprising:

a first base substrate;

a first common electrode on the first base substrate;

a first insulating layer on a side of the first common electrode away from the first base substrate;

a storage capacitor electrode on a side of the first insulating layer away from the first common electrode;

a second insulating layer on a side of the storage capacitor electrode away from the first insulating layer; and

a pixel electrode on a side of the second insulating layer away from the storage capacitor electrode;

wherein orthographic projections of the first common electrode and the pixel electrode on the first base substrate at least partially overlap with each other;

the storage capacitor electrode is electrically connected to one but not the other of the first common electrode and the pixel electrode; and

the first common electrode and the pixel electrode are configured to form a storage capacitor through the storage capacitor electrode.

2. The array substrate of claim 1 , further comprising:

a color resist, over the first base substrate and between the pixel electrode and the storage capacitor electrode.

3. The array substrate of claim 2 , wherein:

the storage capacitor electrode is electrically connected with the pixel electrode through a first via hole extending through the color resist and the second insulating layer.

4. The array substrate of claim 2 , wherein:

the storage capacitor electrode is between the first common electrode and the color resist; and

the storage capacitor electrode is electrically connected with the first common electrode through a second via hole extending through the first insulating layer.

5. The array substrate of claim 2 , further comprising:

an organic film layer between the color resist and the pixel electrode.

6. The array substrate of claim 2 , wherein:

the color resist includes sub-color resists having a gap between adjacent sub-color resists;

the gap is located corresponding to the first common electrode; and

the pixel electrode is at least partially in the gap.

7. The array substrate of claim 6 , wherein:

each sub-color resist in the color resist corresponds to a single sub-pixel.

8. The array substrate of claim 6 , wherein:

a projection of the gap on the first base substrate substantially covers the first common electrode.

9. The array substrate of claim 1 , wherein:

the projection of the storage capacitor electrode on the first base substrate substantially covers the first common electrode.

10. The array substrate of claim 1 , further comprising:

a source/drain electrode, wherein the storage capacitor electrode is in a same layer as the source/drain electrode.

11. The array substrate of claim 1 , further comprising:

a gate electrode, wherein the first common electrode is in a same layer as the gate electrode.

12. A display panel, comprising:

the array substrate according to claim 1 ;

a second base substrate; and

a second common electrode on the second base substrate, wherein the pixel electrode in the array substrate and the second common electrode are placed toward each other to assemble the first base substrate with the second base substrate.

13. A method for forming an array substrate, comprising:

forming a first common electrode on the first base substrate;

forming a first insulating layer on a side of the first common electrode away from the first base substrate;

forming a storage capacitor electrode on a side of the first insulating layer away from the first common electrode;

forming a second insulating layer on a side of the storage capacitor electrode away from the first insulating layer; and

forming a pixel electrode on a side of the second insulating layer away from the storage capacitor electrode;

wherein projections of the first common electrode and the pixel electrode on the first base substrate overlap with each other;

the storage capacitor electrode is formed to be electrically connected to one but not the other of the first common electrode and the pixel electrode; and

the first common electrode and the pixel electrode are configured to form a storage capacitor through the storage capacitor electrode.

14. The method of claim 13 , further comprising:

forming a color resist, over the first base substrate and between the pixel electrode and the storage capacitor electrode.

15. The method of claim 14 , further comprising forming a first via hole extending through the color resist and the second insulating layer;

wherein the storage capacitor electrode is formed to be electrically connected to the pixel electrode through the first via hole.

16. The method of claim 14 , further comprising forming a second via hole extending through the first insulating layer;

wherein the storage capacitor electrode is formed between the first common electrode and the color resist; and

the storage capacitor electrode is formed to be electrically connected with the first common electrode through the second via hole.

17. The method of claim 14 , wherein:

the color resist includes sub-color resists having a gap between adjacent sub-color resists;

the gap is located corresponding to the first common electrode; and

the pixel electrode is at least partially in the gap.

18. The method of claim 17 , wherein:

each sub-color resist in the color resist corresponds to a single sub-pixel; and

a projection of the gap on the first base substrate substantially covers the first common electrode.

19. The method of claim 1 , further comprising:

forming a source/drain electrode, wherein the storage capacitor electrode is in a same layer as the source/drain electrode.

20. The method of claim 1 , further comprising:

forming a gate electrode, wherein the first common electrode is in a same layer as the gate electrode.