Drive control circuit for power semiconductor element
A voltage driver shifts a voltage on a gate as a control terminal of a power semiconductor element in response to an ON command or an OFF command. A gate voltage detector generates a detection signal of a gate-emitter voltage. A delay signal generator generates a delay signal obtained by adding a delay time to the detection signal. A subtractor generates a voltage difference signal between the detection signal and the delay signal. When the voltage difference signal exceeds a reference voltage during an operation of turning on the power semiconductor element, a short-circuit state detector detects a hard-switching fault.
1. A drive control circuit for a power semiconductor element including a control terminal, the drive control circuit comprising:
a driver to operate to shift a voltage on the control terminal in response to an ON command or an OFF command;
a detector configured to detect an electrical quantity of the control terminal;
a delay signal generator configured to generate a delay signal obtained by adding a delay time to a detection signal of the electrical quantity detected by the detector;
a subtractor configured to generate a difference signal between the detection signal and the delay signal; and
a short-circuit state detector configured to detect a short-circuit state in the power semiconductor element based on a result of comparison between the difference signal and a reference value when the driver is operated in response to the ON command.
2. The drive control circuit for a power semiconductor element according to claim 1 , wherein
when a maximum value of the difference signal exceeds the reference value, or when a minimum value of the difference signal becomes lower than the reference value, the short-circuit state detector detects the short-circuit state.
3. The drive control circuit for a power semiconductor element according to claim 1 , further comprising a sample and hold unit configured to, when a first level as a default state is shifted to a second level in response to detection of the short-circuit state by the short-circuit state detector, output a signal holding the second level.
4. The drive control circuit for a power semiconductor element according to claim 1 , further comprising a short-circuit protector configured to generate the OFF command in response to detection of the short-circuit state by the short-circuit state detector.
5. The drive control circuit for a power semiconductor element according to claim 1 , further comprising a soft turn-off unit configured to lower a speed of shifting the electrical quantity by the driver in response to the OFF command, wherein
the soft turn-off unit operates in response to detection of the short-circuit state by the short-circuit state detector.
6. The drive control circuit for a power semiconductor element according to claim 1 , wherein
the power semiconductor element is a voltage-controlled type element that has the control terminal and two main terminals, the control terminal serving as a gate,
the driver is configured to shift a voltage on the gate to a first voltage in response to the ON command, and to shift the voltage on the gate to a second voltage in response to the OFF command, and
the electrical quantity is a gate-emitter voltage.
7. The drive control circuit for a power semiconductor element according to claim 6 , wherein the delay time in the delay signal generator is set to be shorter than an elapsed time period during which the gate-emitter voltage changes from the second voltage to the first voltage by the driver in response to the ON command in a non-short-circuit state.
8. The drive control circuit for a power semiconductor element according to claim 1 , wherein
the power semiconductor element is a voltage-controlled type element that has the control terminal and two main terminals, the control terminal serving as a gate,
the driver operates to shift a voltage on the gate to a first voltage in response to the ON command, and to shift the voltage on the gate to a second voltage in response to the OFF command, and
the electrical quantity is a gate current.
9. The drive control circuit for a power semiconductor element according to claim 8 , wherein the delay time in the delay signal generator is set to be shorter than an elapsed time period from when the ON command is generated until when a voltage across the two main terminals of the power semiconductor element falls to a prescribed voltage, in a state where the driver operates in response to the ON command in a non-short-circuit state.
10. The drive control circuit for a power semiconductor element according to claim 8 , further comprising a determination time period setting unit configured to set a determination time period during which the short-circuit state detector detects the short-circuit state, wherein
the determination time period setting unit is configured to set, as the determination time period, a time period from when the ON command is generated in a non-short-circuit state until when a voltage across the two main terminals of the power semiconductor element falls to a prescribed voltage.
11. The drive control circuit for a power semiconductor element according to claim 1 , further comprising:
an output unit configured to output a signal showing a determination result obtained by the short-circuit state detector; and
an output terminal configured to output a signal from the output unit to an outside.
12. The drive control circuit for a power semiconductor element according to claim 1 , further comprising:
a signal processor to generate a first signal showing a peak value that is a maximum value or a minimum value of the difference signal in response to the difference signal from the subtractor;
a select terminal to input, from an outside of the drive control circuit, a signal for designating at least one of the first signal and a second signal as a signal to be output, the second signal showing a determination result obtained by the short-circuit state detector;
an output unit configured to output at least one signal designated as the signal to be output among the first signal and the second signal in response to an input signal to the select terminal; and
an output terminal configured to output a signal from the output unit to the outside of the drive control circuit.
13. The drive control circuit for a power semiconductor element according to claim 12 , wherein
the first signal is a digital signal including multiple bits that is obtained by analog-to-digital conversion of the peak value,
the second signal is a digital signal showing the determination result, and
the output terminal is configured to output a serial signal including the first signal and the second signal to the outside of the drive control circuit when the input signal designating the first signal and the second signal as the signal to be output is input to the select terminal.