IP Library › Granted Patent US 10,340,279
Granted Patent B2
US 10,340,279 · App. 15/574,771 · Granted Jul 2, 2019

Semiconductor device and method of manufacturing the same

Inventor: Tsunenori Shiimoto (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/11206H01L21/326H01L23/5252H01L27/1157H01L27/11524H01L27/11548H01L27/11556H01L27/11575H01L27/11582G11C16/0483
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Quick Facts
Patent No.
US 10,340,279
App. No.
15/574,771
Granted
Jul 2, 2019
Kind
B2
Abstract

Semiconductors and methods of manufacturing semiconductors are provided. A semiconductor can include a plurality of insulating layers, and a plurality of conductive layers, with the insulating layers and the conductive layers alternately stacked. A plurality of through electrodes penetrate the conductive layers. At least some the through electrodes are electrically connected to one of the conductive layers. In addition, different conductive layers are connected to different through electrodes. A method of forming a semiconductor structure includes providing a plurality of antifuses, wherein each of the through electrodes is separated from each of the conductive layers by an antifuse. The method further includes supplying at least a first voltage to a first through electrode while applying less than a second voltage to the other electrodes, wherein the first voltage is greater than the second voltage.

Claims (51)

1. A method of manufacturing a semiconductor device comprising:

selecting a first through electrode from a plurality of through electrodes, the through electrodes penetrating a plurality of conductive layers and a plurality of insulating layers that are alternately stacked, wherein

antifuses are each provided between corresponding ones of the through electrodes and corresponding ones of the conductive layers;

applying a first voltage and a second voltage, the first voltage being applied to one or more of the through electrodes excluding the first electrode, and the second voltage being applied to the first through electrode; and

causing the first through electrode to be electrically floated after the second voltage is applied to the first through electrode.

2. The method of manufacturing the semiconductor device according to claim 1 , wherein each one of the through electrodes is electrically coupled to corresponding ones of the conductive layers through corresponding ones of the antifuses provided between the ones of the through electrodes and the corresponding ones of the conductive layers.

3. The method of manufacturing the semiconductor device according to claim 1 , wherein

the through electrodes each correspond to any one of the conductive layers,

each of the antifuses provided between the through electrodes and the conductive layers corresponding to each other has a low resistance, and

each of the antifuses provided between the through electrodes and the conductive layers non-corresponding to each other has a high resistance.

4. The method of manufacturing the semiconductor device according to claim 1 , wherein

a first through electrode of the through electrodes is electrically coupled to a first conductive layer of the conductive layers through one of the antifuses provided between the first through electrode and the first conductive layer, and

a second through electrode of the through electrodes is electrically coupled to the first conductive layer through another one of the antifuses provided between the second through electrode and the first conductive layer.

5. The method of manufacturing the semiconductor device according to claim 1 , wherein the number of the through electrodes is greater than the number of the conductive layers.

6. The method of manufacturing the semiconductor device according to claim 1 , wherein the number of the through electrodes is 1.37 times or greater than 1.37 times the number of the conductive layers.

7. A method of manufacturing a semiconductor device comprising:

selecting a first through electrode from a plurality of through electrodes, the through electrodes penetrating a plurality of conductive layers and a plurality of insulating layers that are alternately stacked, wherein

antifuses are each provided between corresponding ones of the through electrodes and corresponding ones of the conductive layers;

applying a first voltage and a second voltage, the first voltage being applied to one or more of the through electrodes excluding the first electrode, and the second voltage being applied to the first through electrode;

selecting a second through electrode from the through electrodes excluding the first through electrode; and

applying the first voltage, the second voltage, and a third voltage, the first voltage being applied to the through electrodes excluding the first through electrode and the second through electrode, the second voltage being applied to the second through electrode, and the third voltage being applied to the first through electrode and being between the first voltage and the second voltage.

8. The method of manufacturing the second device according to claim 7 , further comprising causing the second through electrode to be electrically floated after the second voltage is applied to the second through electrode.

9. The method of manufacturing the semiconductor device according to claim 8 , wherein the applying of the third voltage to the first through electrode is continued when the second through electrode is electrically floated.

10. The method of manufacturing the semiconductor device according to claim 8 , further comprising causing the first through electrode to be electrically floated when the second through electrode is electrically floated.

11. The method of manufacturing the semiconductor device according to claim 7 , wherein

the first voltage is a ground voltage, and

the third voltage is about half of the first voltage.

12. The method of manufacturing the semiconductor device according to claim 7 , wherein each one of the through electrodes is electrically coupled to corresponding ones of the conductive layers through corresponding ones of the antifuses provided between the ones of the through electrodes and the corresponding ones of the conductive layers.

13. The method of manufacturing the semiconductor device according to claim 7 , wherein

the through electrodes each correspond to any one of the conductive layers,

each of the antifuses provided between the through electrodes and the conductive layers corresponding to each other has a low resistance, and

each of the antifuses provided between the through electrodes and the conductive layers non-corresponding to each other has a high resistance.

14. The method of manufacturing the semiconductor device according to claim 7 , wherein

a first through electrode of the through electrodes is electrically coupled to a first conductive layer of the conductive layers through one of the antifuses provided between the first through electrode and the first conductive layer, and

a second through electrode of the through electrodes is electrically coupled to the first conductive layer through another one of the antifuses provided between the second through electrode and the first conductive layer.

15. The method of manufacturing the semiconductor device according to claim 7 , wherein the number of the through electrodes is greater than the number of the conductive layers.

16. The method of manufacturing the semiconductor device according to claim 7 , wherein the number of the through electrodes is 1.37 times or greater than 1.37 times the number of the conductive layers.

17. A method of manufacturing a semiconductor device comprising:

selecting a first through electrode from a plurality of through electrodes, the through electrodes penetrating a plurality of conductive layers and a plurality of insulating layers that are alternately stacked, wherein

antifuses are each provided between corresponding ones of the through electrodes and corresponding ones of the conductive layers;

applying a first voltage and a second voltage, the first voltage being applied to one or more of the through electrodes excluding the first electrode, and the second voltage being applied to the first through electrode;

selecting a third through electrode from unselected through electrodes of the through electrodes; and

applying the first voltage and a fourth voltage, the first voltage being applied to the first through electrode, and the fourth voltage being applied to the third through electrode.

18. The method of manufacturing the semiconductor device according to claim 17 , wherein each one of the through electrodes is electrically coupled to corresponding ones of the conductive layers through corresponding ones of the antifuses provided between the ones of the through electrodes and the corresponding ones of the conductive layers.

19. The method of manufacturing the semiconductor device according to claim 17 , wherein

the through electrodes each correspond to any one of the conductive layers,

each of the antifuses provided between the through electrodes and the conductive layers corresponding to each other has a low resistance, and

each of the antifuses provided between the through electrodes and the conductive layers non-corresponding to each other has a high resistance.

20. The method of manufacturing the semiconductor device according to claim 17 , wherein

a first through electrode of the through electrodes is electrically coupled to a first conductive layer of the conductive layers through one of the antifuses provided between the first through electrode and the first conductive layer, and

a second through electrode of the through electrodes is electrically coupled to the first conductive layer through another one of the antifuses provided between the second through electrode and the first conductive layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 17, 2017
From: SHIIMOTO, TSUNENORI
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 044784/0824 →
Priority Claims (1)
JP 2015-107672 · May 27, 2015 · national
Continuity (1)
Related Publication 20180102371A1 · Apr 12, 2018
Cited By (1)
US 12,490,437