METHOD FOR PRODUCING AN ELECTRONIC COMPONENT WITH A CARRIER ELEMENT AND ELECTRONIC COMPONENT WITH A CARRIER ELEMENT
The invention relates to a method for producing an electronic component with a carrier element ( 100 ), with the steps: producing the carrier element ( 100 ), having the steps A) providing a first metal layer ( 1 ) comprising a first metal material, wherein the first metal layer ( 1 ) has a first and a second main surface ( 10, 11 ) which face away from one another, B) applying a second metal layer ( 2 ) comprising a second metal material on at least one of the main surfaces ( 10, 11 ), C) converting a part of the second metal layer ( 2 ) into a dielectric ceramic layer ( 3 ), wherein the second metal material forms a component of the ceramic layer ( 3 ), and the ceramic layer ( 3 ) forms a surface ( 30 ) which faces away from the first metal layer ( 1 ) and is above the second metal layer ( 2 );—arranging at least one electronic semiconductor chip ( 21 ) on the carrier element ( 100 ). The invention further relates to an electronic component with a carrier element ( 100 ).
1 . A method for producing an electronic component with a carrier element having the following steps:
production of the carrier element, comprising the following steps:
A) providing a first metal layer with a first metal material, wherein the first metal layer comprises a first and a second main surface, which face away from one another,
B) applying a second metal layer with a second metal material on at least one of the main surfaces,
C) converting part of the second metal layer to a dielectric ceramic layer, wherein the second metal material forms part of the ceramic layer and the ceramic layer forms a surface over the second metal layer facing away from the first metal layer;
arranging at least one electronic semiconductor chip on the carrier element.
2 . The method according to claim 1 , in which the first metal material comprises one or more materials selected from copper, nickel, titanium, steel, stainless steel and alloys therewith.
3 . The method according to claim 1 , in which the second metal material comprises aluminum, in particular aluminum with a purity of greater than or equal to 99.99%.
4 . The method according to claim 1 , in which the second metal layer is applied on the first metal layer by means of an electroplating method.
5 . The method according to claim 4 , in which the electroplating method takes place with the exclusion of oxygen and water.
6 . The method according to claim 1 , in which the ceramic layer is produced by means of electrolytic oxidation.
7 . The method according to claim 1 , in which the second metal layer is applied directly on the first metal layer.
8 . The method according to claim 1 , in which the second metal layer and the ceramic layer are applied over a large area and coherently on at least one of the main surfaces of the first metal layer.
9 . The method according to claim 1 , in which a patterned third metal layer is applied on the ceramic layer, wherein a seed layer is applied directly on the ceramic layer, on which seed layer the third metal layer is applied by means of an electroplating method.
10 . The method according to claim 9 , in which the patterned third metal layer at least partly forms patterned contact surfaces and/or traces.
11 . The method according to claim 1 , in which the first metal layer is provided with at least one opening and the second metal layer and the ceramic layer are applied on a wall surface of the opening.
12 . The method according to claim 11 , in which a third metal layer is applied on the ceramic layer on the wall surface of the opening to form an electrical feed-through, which passes through the first metal layer and through the second metal layer and the ceramic layer on the at least one main surface of the first metal layer.
13 . The method according to claim 1 , in which method steps B and C are performed on each of the two main surfaces.
14 . An electronic component comprising a carrier element and at least one electronic semiconductor chip on the carrier element, the carrier element comprising
a first metal layer with a first metal material and with a first and second main surface, which face away from one another,
on at least one of the main surfaces a second metal layer with a second metal material and
on the second metal layer a dielectric ceramic layer, wherein the second metal material forms part of the ceramic layer and the ceramic layer forms a surface over the second metal layer facing away from the first metal layer.
15 . The electronic component according to claim 14 , wherein the first metal material comprises one or more materials selected from copper, nickel, titanium, steel, stainless steel and alloys therewith and the second metal material comprises aluminum, in particular aluminum with a purity of greater than or equal to 99.99%.
16 . The electronic component according to claim 14 , wherein the second metal layer is arranged directly on the first metal layer and the ceramic layer is arranged directly on the second metal layer.
17 . The electronic component according to claim 14 , wherein on the ceramic layer a patterned third metal layer is arranged, which at least partly forms patterned contact surfaces and/or traces.
18 . The electronic component according to claim 14 , wherein
the first metal layer comprises at least one opening,
the second metal layer and the ceramic layer are arranged on a wall surface of the opening and
a third metal layer is arranged on the ceramic layer on the wall surface of the opening to form an electrical feed-through, which passes through the first metal layer and through the second metal layer and the ceramic layer on the at least one main surface of the first metal layer.
19 . The electronic component according to claim 14 , wherein the carrier element comprises on each of the main surfaces of the first metal layer a second metal layer, and over this a ceramic layer.
20 . The method according to claim 1 , in which a patterned third metal layer is applied on the ceramic layer, which at least partly forms patterned contact surfaces and/or traces through which the electronic semiconductor chip is electrically connected.