Low-dropout voltage regulator apparatus
A low-dropout voltage regulator (LDO) apparatus is disclosed. In an embodiment, the LDO apparatus includes a voltage input connectable to a power supply, an error amplifier coupled to the voltage input and configured to receive a reference signal and a feedback signal and to generate an output control signal dependent on the reference signal and the feedback signal, and a pass transistor coupled to the error amplifier and configured to receive the output control signal of the error amplifier and to provide an output current dependent on the output control signal. The LDO apparatus further includes a detection circuit coupled to the voltage input and configured to provide an output signal on its output and a bias generator coupled to the output of the detection circuit and configured to provide a bias current on a bias input of the current adjusting circuit of the error amplifier.
1. A low-dropout voltage regulator (LDO) apparatus comprising:
a voltage input connectable to a power supply;
an error amplifier coupled to the voltage input and configured to receive a reference voltage signal and a feedback signal and to generate an output control signal dependent on the reference voltage signal and the feedback signal, wherein the error amplifier comprises a current adjusting circuit;
a pass transistor coupled to the error amplifier and configured to receive the output control signal of the error amplifier and to provide an output current for an output of the low-dropout voltage regulator (LDO) apparatus dependent on the output control signal;
a detection circuit coupled to the voltage input and configured to monitor an input voltage provided on the voltage input of the low-dropout voltage regulator (LDO) apparatus and to provide an output signal on its output dependent on the input voltage provided on the voltage input of the low-dropout voltage regulator (LDO) apparatus; and
a bias generator coupled to the output of the detection circuit and configured to provide a bias current on a bias input of the current adjusting circuit of the error amplifier dependent on the output signal of the detection circuit,
wherein the low-dropout voltage regulator (LDO) apparatus comprises an on-chip output capacitor, and
wherein the bias current is proportional to a voltage difference between the input voltage of the low-dropout voltage regulator (LDO) apparatus and a given reference voltage.
2. The low-dropout voltage regulator (LDO) apparatus according to claim 1 , wherein the current adjusting circuit comprises a current mirror circuit configured and arranged to mirror the bias current of the bias generator to the error amplifier.
3. A digital system comprising a digital core and a low-dropout voltage regulator (LDO) apparatus, the low-dropout voltage regulator (LDO) apparatus comprising:
a voltage input;
an error amplifier coupled to the voltage input and configured to receive a reference voltage signal and a feedback signal and to generate an output control signal dependent on the reference voltage signal and the feedback signal, wherein the error amplifier comprises a current adjusting circuit;
a pass transistor coupled to the error amplifier and configured to receive the output control signal of the error amplifier and to provide an output current for an output of the low-dropout voltage regulator (LDO) apparatus dependent on the output control signal;
a detection circuit coupled to the voltage input and configured to monitor an input voltage provided on the voltage input of the low-dropout voltage regulator (LDO) apparatus and to provide an output signal on its output dependent on an input voltage provided on the voltage input of the low-dropout voltage regulator (LDO) apparatus; and
a bias generator coupled to the output of the detection circuit and configured to provide a bias current on a bias input of the current adjusting circuit of the error amplifier dependent on the output signal of the detection circuit,
wherein the voltage input of the low-dropout voltage regulator (LDO) apparatus is coupled to a battery supply and the output of the low-dropout voltage regulator (LDO) apparatus is coupled to the digital core,
wherein the bias current is proportional to a voltage difference between the input voltage of the low-dropout voltage regulator (LDO) apparatus and a given reference voltage.
4. The digital system according to claim 3 , wherein the current adjusting circuit comprises a current mirror circuit configured and arranged to mirror the bias current of the bias generator to the error amplifier.
5. The digital system according to claim 3 , wherein the low-dropout voltage regulator (LDO) apparatus comprises an on-chip output capacitor.
6. A low-dropout voltage regulator (LDO) apparatus comprising:
a voltage input connectable to a power supply;
an error amplifier coupled to the voltage input and configured to receive a reference voltage signal and a feedback signal and to generate an output control signal dependent on the reference voltage signal and the feedback signal, wherein the error amplifier comprises a current adjusting circuit;
a pass transistor coupled to the error amplifier and configured to receive the output control signal of the error amplifier and to provide an output current for an output of the low-dropout voltage regulator (LDO) apparatus dependent on the output control signal;
a detection circuit coupled to the voltage input and configured to provide an output signal on its output dependent on an input voltage provided on the voltage input of the low-dropout voltage regulator (LDO) apparatus; and
a bias generator coupled to the output of the detection circuit and configured to provide a bias current on a bias input of the current adjusting circuit of the error amplifier dependent on the output signal of the detection circuit,
wherein the bias current is proportional to a voltage difference between the input voltage of the low-dropout voltage regulator (LDO) apparatus and a given reference voltage.
7. The low-dropout voltage regulator (LDO) apparatus according to claim 6 , wherein the current adjusting circuit comprises a current mirror circuit configured and arranged to mirror the bias current of the bias generator to the error amplifier.
8. The low-dropout voltage regulator (LDO) apparatus according to claim 6 , wherein the low-dropout voltage regulator (LDO) apparatus comprises an on-chip output capacitor.