Prevention of extension narrowing in nanosheet field effect transistors
Semiconductor devices and methods of forming the same include forming a stack of layers of alternating materials, including first layers of sacrificial material and second layers of channel material. The first layers are recessed relative to the second layers with an etch that etches the second layers at a slower rate than the first layers to taper ends of the second layers. First spacers are formed in recesses formed by recessing the first layers. Second spacers are formed in recesses formed by recessing the first layers. The first spacers are etched to expose sidewalls of the second spacer. Source/drain extensions are formed in contact with exposed ends of the second layers.
1. A semiconductor device, comprising:
a plurality of semiconductor layers;
a source and drain extension formed at respective ends of the one or more semiconductor layers;
a gate stack formed on and around the plurality of semiconductor layers; and
spacers formed between vertically adjacent semiconductor layers, each spacer comprising a first spacer layer and a second spacer layer, the first spacer layer being positioned between the gate stack and the second spacer layer and the second spacer layer of each spacer having a trapezoidal cross-section.
2. The semiconductor device of claim 1 , wherein the plurality of semiconductor layers have tapered ends that align horizontally with ends of the spacers.
3. The semiconductor device of claim 2 , wherein the source and drain extensions fill a space between the tapered ends of the semiconductor layers and the spacers.
4. The semiconductor device of claim 1 , wherein the plurality of semiconductor layers are recessed with respect to the spacers.
5. The semiconductor device of claim 4 , wherein the source and drain extensions fill a space between the second spacer layer of vertically adjacent spacers.
6. The semiconductor device of claim 4 , wherein a portion of first spacer layer remains on an upper surface of the uppermost spacers and wherein a portion of first spacer layer remains on a lower surface of the lowermost spacers.
7. The semiconductor device of claim 1 , wherein the first spacer layer of each spacer is disposed directly on a sidewall of the gate stack.
8. The semiconductor device of claim 7 , wherein the second spacer layer of each spacer is disposed directly on a sidewall of a respective first spacer layer.
9. The semiconductor device of claim 5 , wherein portions of the source and drain extensions on the plurality of semiconductor layers have a trapezoidal cross-section.
10. The semiconductor device of claim 1 , wherein at least a portion of at least one of the first spacer layer of each spacer is forming between vertically adjacent semiconductor layers.
11. A semiconductor device, comprising:
a plurality of semiconductor layers;
a source and drain extension formed at respective ends of the one or more semiconductor layers;
a gate stack formed on and around the plurality of semiconductor layers; and
spacers formed between vertically adjacent semiconductor layers, each spacer comprising a first spacer layer and a second spacer layer, the first spacer layer being positioned between the gate stack and the second spacer layer and the second spacer layer of each spacer having a trapezoidal cross-section, wherein the source and drain extensions fill a space within a perimeter defined by adjacent surfaces of the semiconductor layers and the spacers.
12. The semiconductor device of claim 11 , wherein the first spacer layer of each spacer is disposed directly on a sidewall of the gate stack.
13. The semiconductor device of claim 12 , wherein the second spacer layer of each spacer is disposed directly on a sidewall of a respective first spacer layer.
14. A semiconductor device, comprising:
a plurality of semiconductor layers;
a source and drain extension formed at respective ends of the one or more semiconductor layers;
a gate stack formed on and around the plurality of semiconductor layers; and
spacers formed between vertically adjacent semiconductor layers, each spacer comprising a first spacer layer and a second spacer layer, the first spacer layer being positioned between the gate stack and the second spacer layer and the second spacer layer of each spacer having a trapezoidal cross-section, wherein the source and drain extensions fill a space within a perimeter defined by adjacent surfaces of the second spacer layer of vertically adjacent spacers.
15. The semiconductor device of claim 14 , wherein the first spacer layer of each spacer is disposed directly on a sidewall of the gate stack.
16. The semiconductor device of claim 15 , wherein the second spacer layer of each spacer is disposed directly on a sidewall of a respective first spacer layer.
17. The semiconductor device of claim 14 , wherein portions of the source and drain extensions on the plurality of semiconductor layers have a trapezoidal cross-section.