Termination implant enrichment for shielded gate MOSFETs

1. A power semiconductor device comprising:

a semiconductor region having an active region and a termination region;

a first trench shield electrode defined in the semiconductor region, the first trench shield electrode extending along a first longitudinal axis, the first trench shield electrode having a first portion disposed in the active region and a second portion disposed in the termination region;

a second trench shield electrode defined in the semiconductor region, the second trench shield electrode extending along the first longitudinal axis in parallel with the first trench shield electrode, the second trench shield electrode having a first portion disposed in the active region and a second portion disposed in the termination region, a trench of the first trench shield electrode and a trench of the second trench shield electrode defining a mesa of the semiconductor region therebetween; and

an implant enrichment region disposed in the termination region, the implant enrichment region extending along a second longitudinal axis that is orthogonal with the first longitudinal axis,

the implant enrichment region being intersected by the first trench shield electrode and the second trench shield electrode, and having a portion disposed in the mesa of the semiconductor region, the portion extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.

2. The power semiconductor device of claim 1 , wherein:

the semiconductor region is of a first conductivity type, the semiconductor region having a doping concentration that increases over a depth of the semiconductor region from a surface of the semiconductor region;

the implant enrichment region is of the first conductivity type and has a surface doping concentration that is greater than a surface doping concentration of the semiconductor region; and

the active region includes a well region of a second conductivity type that is opposite the first conductivity type.

3. The power semiconductor device of claim 2 , wherein the first conductivity type is N-type and the second conductivity type is p-type.

4. The power semiconductor device of claim 1 , wherein the implant enrichment region is:

spaced, along the first longitudinal axis, a first distance from the active region; and

spaced, along the first longitudinal axis, a second distance from respective ends of the first trench shield electrode and the second shield electrode.

5. The power semiconductor device of claim 1 , wherein the implant enrichment region is a first implant enrichment region, the power semiconductor device further comprising:

a second implant enrichment region disposed in the termination region between the first implant enrichment region and the active region, the second implant enrichment region extending along the second longitudinal axis in parallel with the first implant enrichment region, the second implant enrichment region being intersected by the first trench shield electrode and the second trench shield electrode, the second implant enrichment region having a portion disposed in the mesa of the semiconductor region, the portion of the second implant enrichment region extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.

6. The power semiconductor device of claim 5 , wherein:

the first implant enrichment region has a first width along the first longitudinal axis; and

the second implant enrichment region has a second width along the first longitudinal axis,

the second width being different than the first width.

7. The power semiconductor device of claim 6 , wherein the second width is less than the first width.

8. The power semiconductor device of claim 5 , further comprising:

a third implant enrichment region disposed in the termination region between the second implant enrichment region and the active region, the third implant enrichment region extending along the second longitudinal axis in parallel with the first implant enrichment region and the second implant enrichment region, the third implant enrichment region being intersected by the first trench shield electrode and the second trench shield electrode, the third implant enrichment region having a portion disposed in the mesa of the semiconductor region, the portion of the third implant enrichment region extending from the trench of the first trench shield electrode to the trench of the second trench shield electrode.

9. The power semiconductor device of claim 8 , wherein:

the first implant enrichment region has a first width along the first longitudinal axis;

the second implant enrichment region has a second width along the first longitudinal axis; and

the third implant enrichment region has a third width along the first longitudinal axis,

the third width being less than the second width, and the second width being less than the first width.

10. The power semiconductor device of claim 8 , wherein the first implant enrichment region, the second implant enrichment region and the third implant enrichment region have a same implant dose.

11. The power semiconductor device of claim 1 , wherein:

the implant enrichment region has a first depth from a surface of the semiconductor region; and

the first trench shield electrode and the second trench shield electrode have a second depth from the surface of the semiconductor region,

the first depth being less than the second depth.

12. The power semiconductor device of claim 11 , wherein the first depth is less than or equal to 6 micrometers (μm) and the second depth is greater than or equal to 6 μm.

13. The power semiconductor device of claim 1 , wherein the first trench shield electrode includes a recessed portion disposed at an end of the first trench shield electrode in the termination region, the recessed portion of the first trench shield electrode being filled with a dielectric.

14. A power semiconductor device comprising:

a semiconductor region having an active region and a termination region;

a first implant enrichment region disposed in the termination region, the first implant enrichment region extending along a first longitudinal axis;

a second implant enrichment region disposed in the termination region, the second implant enrichment region extending along the first longitudinal axis and in parallel with the first implant enrichment region, the second implant enrichment region being disposed between the first implant enrichment region and the active region;

a first trench shield electrode defined in the semiconductor region, the first trench shield electrode extending along a second longitudinal axis that is orthogonal with the first longitudinal axis, the first trench shield electrode having a first portion disposed in the active region and a second portion disposed in the termination region; and

a second trench shield electrode defined in the semiconductor region, the second trench shield electrode extending along the second longitudinal axis in parallel with the first trench shield electrode, the second trench shield electrode having a first portion disposed in the active region and a second portion disposed in the termination region, a trench of the first trench shield electrode and a trench of the second trench shield electrode defining a first mesa of the semiconductor region therebetween,

the first trench shield electrode and the second trench shield electrode each intersecting the first implant enrichment region and the second implant enrichment region, a first portion of the first implant enrichment region and a first portion of the second implant enrichment region being disposed in the first mesa of the semiconductor region.

15. The power semiconductor device of claim 14 , further comprising:

a third trench shield electrode defined in the semiconductor region, the third trench shield electrode extending along the second longitudinal axis in parallel with the first trench shield electrode and the second trench shield electrode, the third trench shield electrode having a first portion disposed in the active region and a second portion disposed in the termination region, the trench of the second trench shield electrode and a trench of the third trench electrode defining a second mesa of the semiconductor region therebetween,

the third trench shield electrode intersecting the first implant enrichment region and the second implant enrichment region, a second portion of the first implant enrichment region and a second portion of the second implant enrichment region being disposed in the second mesa of the semiconductor region.

16. The power semiconductor device of claim 14 , wherein the semiconductor region includes an epitaxial layer having a graded doping concentration that increases, from an upper mesa surface to a bottom of the trench.

17. The power semiconductor device of claim 14 , further comprising:

a third implant enrichment region disposed in the termination region, the third implant enrichment region extending along the second longitudinal axis and in parallel with the first implant enrichment region and the second implant enrichment region, the third implant enrichment region being disposed between the second implant enrichment region and the active region,

the first trench shield electrode and the second trench shield electrode each intersecting the third implant enrichment region, a portion of the third implant enrichment region being disposed in the first mesa of the semiconductor region.

18. The power semiconductor device of claim 14 , wherein the first implant enrichment region and the second implant enrichment region have an N-type implant dose of greater than or equal to 2.5×10 13 /cm 2 .

19. The power semiconductor device of claim 14 , wherein the first trench shield electrode includes a recessed portion disposed at an end of the first trench shield electrode in the termination region, the recessed portion of the first trench shield electrode being filled with a dielectric.