IP Library Granted Patent US 10,291,052
Granted Patent B2
US 10,291,052 · App. 15/582,988 · Granted May 14, 2019

Bypass charging circuit and method

Inventors: James A. Meacham, II (Gorham, ME); Karttikeya Shah (Fremont, CA)
Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
H02J7/0083H02J7/0029H02J7/0031H02J7/0045H02J7/0047H02J7/0077H02J7/0081
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Quick Facts
Patent No.
US 10,291,052
App. No.
15/582,988
Granted
May 14, 2019
Kind
B2
Abstract

In accordance with an embodiment, a bypass charging circuit includes a pair of transistors having current carrying terminals commonly connected to form a node. An input of a comparator is coupled to the node through a switch and to a resistor. Another input terminal of the comparator is coupled for receiving a reference voltage. Optionally, a transistor may be connected to the bypass charging circuit. In accordance with another embodiment a method is provided in which bypass charging transistors are coupled to first input of a comparator in response to closing a switch. A voltage is generated at the first input of the comparator in response to closing the switch and the voltage is compared with a reference voltage. In response to the comparison, a status indicator signal is generated to indicate the presence of a low-impedance failure in one or both of the bypass charging transistors.

Claims (37)

1. A bypass charging circuit that includes a failure detection section, comprising:

a first transistor having a control terminal, a first current carrying terminal, and a second current carrying terminal;

a second transistor having a control terminal, a first current carrying terminal, and a second current carrying terminal, the first current carrying terminal of the second transistor directly coupled to the second current carrying terminal of the first transistor to form a first node that is between the first transistor and the second transistor;

a comparator having a first input, a second input, and an output, the first input of the comparator coupled to the first node and the second input of the comparator coupled for receiving a reference potential; and

a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the first input of the comparator.

2. The bypass charging circuit of claim 1 , further including a first switch having a control terminal, a first conduction terminal, and a second conduction terminal, the first conduction terminal of the first switch coupled to the first node and the second conduction terminal of the first switch coupled to the first input of the comparator.

3. The bypass charging circuit of claim 2 , further including a third transistor having a control terminal, a first current carrying terminal, and a second current carrying terminal, the first current carrying terminal of the third transistor coupled to the first current carrying terminal of the first transistor.

4. The bypass charging circuit of claim 3 , wherein the control terminal of the first transistor is coupled to the control terminal of the second transistor.

5. The bypass charging circuit of claim 4 , further including a control circuit having a first input/output, a second input, a first output, a second output, and a third output, wherein the first output of the control circuit is coupled to the control terminals of the first transistor and the second transistor, the second output of the control circuit is coupled to the control terminal of the first switch, and the third output of the control circuit is coupled to the control terminal of the third transistor.

6. The bypass charging circuit of claim 5 , further including a first diode having an anode and a cathode, the anode of the first diode coupled to the first current carrying terminal of the third transistor and the cathode of the third diode coupled to the second current carrying terminal of the third transistor.

7. The bypass charging circuit of claim 2 , further including a control circuit having a first input, a second input, a first output, a second output, and a third output, wherein the first output of the control circuit is coupled to the control terminal of the first transistor, the second output of the control circuit is coupled to the control terminal of the first switch, the third output of the control circuit is coupled to the control terminal of the second transistor, and the output of the comparator is coupled to the second input of the control circuit.

8. The bypass charging circuit of claim 7 , wherein the first input terminal of the control circuit is an input/output terminal.

9. The bypass charging circuit of claim 1 , further including:

a first diode having an anode and a cathode, the anode of the first diode coupled to the second current carrying terminal of the first transistor and the cathode of the first diode coupled to the first current carrying terminal of the first transistor; and

a second diode having an anode and a cathode, the anode of the second diode coupled to the first current carrying terminal of the second transistor and the cathode of the second diode coupled to the second current carrying terminal of the second transistor.

10. The bypass charging circuit of claim 1 , wherein the second current carrying terminal of the second transistor is configured for coupling to a battery.

11. A method for detecting failure of a bypass charging circuit, comprising:

providing bypass charging transistors comprising first and second transistors, each transistor of the first and second transistors having a control terminal, a first current carrying terminal, and a second current carrying terminal, the first current carrying terminal of the second transistor directly coupled to the second current carrying terminal of the first transistor to form a first node that is between the first transistor and the second transistor;

coupling the first node formed by the bypass charging transistors to a first input of a comparator in response to closing a switch, wherein the comparator and the switch form a portion of a failure detection section;

developing a first voltage at the first input of the comparator in response to closing the switch;

comparing the first voltage with a reference voltage; and

generating a status indicator signal in response to comparing the first voltage with the reference voltage.

12. The method of claim 11 , wherein developing the first voltage at the first input of the comparator includes developing the first voltage in response to a current flowing through a resistor.

13. The method of claim 12 , wherein generating the status indicator signal includes generating the status indicator signal to indicate failure of the bypass charging circuit in response to the first voltage being greater than the reference voltage.

14. The method of claim 12 , wherein generating the status indicator signal includes generating the status indicator signal to indicate the bypass charging circuit is in condition to charge a battery in response to the first voltage being less than the reference voltage.

15. The method of claim 12 , further including opening the switch in response to the status indicator signal indicating failure of the bypass charging circuit.

16. The method of claim 12 , further including electrically disconnecting the battery charging circuit from a signal source in response to the status indicator signal indicating failure of the bypass charging circuit.

17. The method of claim 16 , wherein electrically disconnecting the battery charging circuit from the signal source includes generating a control signal to turn off a transistor between the bypass charging circuit and the signal source.

18. A method for detecting failure of a bypass charging circuit, comprising:

providing first and second transistors, each transistor of the first and second transistors having a control terminal, a first current carrying terminal, and a second current carrying terminal, the first current carrying terminal of the second transistor directly coupled to the second current carrying terminal of the first transistor to form a first node that is between the first transistor and the second transistor;

closing a first switch in response to a control signal, wherein closing the first switch couples the first node to an input of a comparator;

generating a first voltage at the first input of the comparator;

comparing the first voltage at the first input of the comparator with a second voltage at a second input of the comparator;

generating a comparison voltage at the output of the comparator in response to comparing the first voltage with the second voltage;

using the comparison voltage to determine whether the bypass charging circuit has failed.

19. The method of claim 18 , further including turning off a third transistor coupled to the first current carrying terminal of the first transistor in response to the comparison signal indicating that the bypass charging circuit has failed.

20. The method of claim 18 , wherein generating the first voltage further includes turning off the first transistor and the second transistor.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 044481, FRAME 0594 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064074/0363 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0594 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2017
From: MEACHAM II, JAMES A.; SHAH, KARTTIKEYA
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 042192/0627 →
Continuity (2)
Provisional Application 62341454 · May 25, 2016
Related Publication 20170346328A1 · Nov 30, 2017