IP Library Patent Application 15584294
Patent Application
App. No. 15/584,294

INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES

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Quick Facts
Patent No.
US None
App. No.
15/584,294
Abstract

A semiconductor device comprising a substrate is provided. The device further comprises a through-substrate via (TSV) extending into the substrate, and a substantially helical conductor disposed around the TSV. The substantially helical conductor can be configured to generate a magnetic field in the TSV in response to a current passing through the helical conductor. More than one TSV can be included, and/or more than one substantially helical conductor can be provided.

Claims (51)

1 . A semiconductor device, comprising:

a substrate,

a through-substrate via (TSV) extending into the substrate, and

a substantially helical conductor disposed around the TSV.

2 . The semiconductor device of claim 1 , wherein the substantially helical conductor is configured to generate a magnetic field in the TSV in response to a current passing through the substantially helical conductor.

3 . The semiconductor device of claim 2 , wherein the substantially helical conductor is configured to induce a change in the magnetic field in the TSV in response to a changing current in the substantially helical conductor.

4 . The semiconductor device of claim 1 , wherein the TSV comprises a ferromagnetic or a ferrimagnetic material.

5 . The semiconductor device of claim 1 , wherein the TSV is separated from the substantially helical conductor by an insulating material.

6 . The semiconductor device of claim 1 , wherein the substantially helical conductor comprises more than one turn around the TSV.

7 . The semiconductor device of claim 1 , wherein the substantially helical conductor is coaxially aligned with the TSV.

8 . A semiconductor device, comprising:

a substrate,

a through-substrate via (TSV) extending into the substrate,

a first substantially helical conductor disposed around the TSV, and

a second substantially helical conductor disposed around the TSV.

9 . The semiconductor device of claim 8 , wherein the first substantially helical conductor is configured to induce a change in a magnetic field in the TSV in response to a first changing current in the first substantially helical conductor, and wherein the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field.

10 . The semiconductor device of claim 9 , further comprising:

a third substantially helical conductor disposed around the TSV,

wherein the third substantially helical conductor is configured to have a third changing current induced therein in response to the change in the magnetic field.

11 . The semiconductor device of claim 8 , wherein the TSV comprises a ferromagnetic or a ferrimagnetic material.

12 . The semiconductor device of claim 8 , wherein the TSV is separated from the first and second substantially helical conductors by an insulating material.

13 . The semiconductor device of claim 8 , wherein the first substantially helical conductor comprises a different number of turns around the TSV than the second substantially helical conductor.

14 . The semiconductor device of claim 8 , wherein the first and second substantially helical conductors comprise a same number of turns around the TSV.

15 . The semiconductor device of claim 8 , wherein one of the first and second substantially helical conductors comprises more than one turn around the TSV.

16 . The semiconductor device of claim 8 , wherein the first and second substantially helical conductors are coaxially aligned with the TSV.

17 . The semiconductor device of claim 8 , wherein the first substantially helical conductor and the second substantially helical conductor are electrically isolated from each other and from the TSV.

18 . The semiconductor device of claim 8 , wherein the first substantially helical conductor is electrically connected to a power supply and the second substantially helical conductor is electrically connected to a load.

19 . A semiconductor device, comprising:

a substrate,

a first through-substrate via (TSV) extending into the substrate,

a second TSV extending into the substrate,

a first substantially helical conductor disposed around the first TSV, and

a second substantially helical conductor disposed around the second TSV.

20 . The semiconductor device of claim 19 , wherein the first substantially helical conductor is configured to induce a change in a magnetic field in the first TSV and the second TSV in response to a first changing current in the first substantially helical conductor, and wherein the second substantially helical conductor is configured to have a second changing current induced therein in response to the change in the magnetic field in the second TSV.

21 . The semiconductor device of claim 20 wherein the first TSV is coupled to the second TSV by an upper coupling member above the first and second substantially helical conductors, and by a lower coupling member below the first and second substantially helical conductors, such that the first and second TSVs and the upper and lower coupling members form a closed path for the magnetic field.

22 . The semiconductor device of claim 19 , wherein each of the first and second TSVs comprise a ferromagnetic or a ferrimagnetic material.

23 . The semiconductor device of claim 19 , wherein the first TSV is electrically insulated from the first substantially helical conductor, and the second TSV is electrically insulated from the second substantially helical conductor.

24 . The semiconductor device of claim 19 , wherein the first substantially helical conductor and the second substantially helical conductor are electrically isolated from each other and from the first and second TSVs.

25 . The semiconductor device of claim 19 , wherein the first substantially helical conductor comprises a different number of turns around the first TSV than the second substantially helical conductor comprises around the second TSV.

26 . The semiconductor device of claim 19 , wherein the first substantially helical conductor comprises a same number of turns around the first TSV as the second substantially helical conductor comprises around the second TSV.

27 . The semiconductor device of claim 19 , wherein the first substantially helical conductor comprises more than one turn around the first TSV.

28 . The semiconductor device of claim 19 , wherein the second substantially helical conductor comprises more than one turn around the second TSV.

29 . The semiconductor device of claim 19 , wherein the first substantially helical conductor is coaxially aligned with the first TSV, and the second substantially helical conductor is coaxially aligned with the second TSV.

30 . The semiconductor device of claim 19 , wherein the first substantially helical conductor is electrically connected to a power supply and the second substantially helical conductor is electrically connected to a load.

31 . A semiconductor device, comprising:

a substrate,

a through-substrate via (TSV) extending into the substrate, and

a non-planar spiral conductor disposed around the TSV.

32 . The semiconductor device of claim 31 , wherein the non-planar spiral conductor is configured to generate a magnetic field in the TSV in response to a current passing through the non-planar spiral conductor.

33 . The semiconductor device of claim 32 , wherein the non-planar spiral conductor is configured to induce a change in the magnetic field in the TSV in response to a changing current in the non-planar spiral conductor.

34 . The semiconductor device of claim 31 , wherein the TSV comprises a ferromagnetic or a ferrimagnetic material.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050709/0838 →
RELEASE OF SECURITY INTEREST Recorded Jul 20, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 046597/0333 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 044348/0253 →
SUPPLEMENT NO. 6 TO PATENT SECURITY AGREEMENT Recorded Nov 1, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 044653/0333 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2017
From: KIRBY, KYLE K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042210/0029 →