Ramp generator for wide frequency range pulse width modulator controller or the like

1. A ramp generator, comprising:

a current generator having an input for receiving a clock signal, and an output for providing a current proportional to a frequency of said clock signal, said current generator comprising:

a first transistor having a first current electrode for providing said current, a second current electrode, and a control electrode;

an amplifier having a non-inverting input for receiving a reference voltage, an inverting input coupled to said second current electrode of said first transistor, and an output coupled to said control electrode of said first transistor; and

a variable resistor having a first terminal coupled to said second current electrode of said first transistor, a second terminal coupled to a first power supply voltage terminal, and a control terminal for receiving said clock signal,

a current mirror having an input coupled to said first terminal of said first transistor, and an output; and

a first capacitor having a first terminal coupled to said output of said current mirror and providing a ramp signal, and a second terminal coupled to said first power supply voltage terminal.

2. The ramp generator of claim 1 , wherein said variable resistor comprises a switched capacitor resistor.

3. The ramp generator of claim 2 , wherein said variable resistor comprises:

a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving a complement of said clock signal, and a second current electrode;

a second capacitor having a first terminal coupled to said second current electrode of said second transistor, and a second terminal coupled to said first power supply voltage terminal; and

a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving said clock signal, and a second current electrode coupled to said first power supply voltage terminal.

4. The ramp generator of claim 3 , further comprising:

a clock circuit having a first output for providing said clock signal, a second output for providing said complement of said clock signal, and a third output for providing a divided clock signal; and

a fourth transistor having a first current electrode coupled to said first terminal of said first capacitor, a control electrode coupled to said third output of said clock circuit, and a second current electrode coupled to said first power supply voltage terminal.

5. The ramp generator of claim 4 , further comprising:

a narrow pulse generator coupled between said third output of said clock circuit and said control electrode of said fourth transistor and responsive to said divided clock signal for providing a narrow clock pulse to said control electrode of said fourth transistor wherein said narrow clock pulse has a rising edge aligned with a rising edge of said divided clock signal, and an active period less than an active period of said divided clock signal.

6. The ramp generator of claim 5 , further comprising:

a first current source having a first terminal coupled to said second current electrode of said first transistor, and a second terminal coupled to said first power supply voltage terminal; and

a second current source having a first terminal coupled to said first terminal of said first capacitor, and a second terminal coupled to said first power supply voltage terminal.

7. The ramp generator of claim 1 , further comprising:

a first resistor having a first terminal for receiving an input voltage, and a second terminal coupled to said non-inverting input of said amplifier for providing said reference voltage; and

a second resistor having a first terminal coupled to said second terminal of said first resistor, and a second terminal coupled to said first power supply voltage terminal.

8. The ramp generator of claim 1 , wherein said current mirror comprises:

a fifth transistor having a first current electrode coupled to a second power supply voltage terminal, a control electrode, and a second current electrode coupled to said control electrode thereof and to said first current electrode of said first transistor; and

a sixth transistor having a first current electrode coupled to said second power supply voltage terminal, a control electrode coupled to said second current electrode of said fifth transistor, and a second current electrode coupled to said first terminal of said first capacitor.

9. The ramp generator of claim 8 , wherein said second current electrode of said fifth transistor is coupled to said control electrode of said sixth transistor through a direct current (DC) filter.

10. A method comprising:

setting a value of a variable resistor according to a frequency of a first clock signal;

generating an input current according to said value of said variable resistor;

mirroring said input current to form a ramp current proportional to said input current; and

alternately charging a first capacitor using said ramp current and discharging said first capacitor in synchronism with a second clock signal; and

forming a ramp signal from a voltage on said first capacitor.

11. The method of claim 10 wherein said setting said value of said variable resistor comprises:

switching a first terminal of a second capacitor to a first terminal of said variable resistor in response to a complement of said first clock signal; and

switching said first terminal of said second capacitor to a power supply voltage terminal in response to said first clock signal.

12. The method of claim 11 , further comprising:

discharging said first capacitor in synchronism with a divided clock signal formed by dividing said first clock signal.

13. The method of claim 10 wherein said generating said input current comprises:

providing said input current from a first current electrode of a first transistor; and

biasing a control electrode of said first transistor according to a difference between a reference voltage and a voltage on a second current electrode of said first transistor.

14. The method of claim 13 , further comprising:

forming said reference voltage as a proportion of an input voltage.

15. The method of claim 10 , further comprising:

using said ramp signal to form an output voltage in a switch mode power supply.