Sense amplifier with offset compensation

1. An amplifier circuit comprising:

an amplifier having first and second input terminals;

a first compensation capacitor coupled to the first input terminal and having a first capacitance;

a second compensation capacitor coupled to the second input terminal and having a second capacitance;

a first transistor source-drain coupled between the first compensation capacitor and a reference voltage and having a gate terminal for receiving a first control signal;

a second transistor source-drain coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal; and

a programmable latch circuit arranged to provide the first and second control signals;

wherein the first and second transistors are of the same conductivity type, and the first and second control signals are complementary signals with respect to each other.

2. The amplifier circuit of claim 1 , comprising:

a third compensation capacitor coupled to the first input terminal and having a third capacitance;

a fourth compensation capacitor coupled to the second input terminal and having a fourth capacitance;

a third transistor source-drain coupled between the third compensation capacitor and the reference voltage and having a gate terminal for receiving a third control signal; and

a fourth transistor source-drain coupled between the fourth compensation capacitor and the reference voltage and having a gate terminal for receiving a fourth control signal;

wherein the programmable latch circuit is arranged to provide the third and fourth control signals, wherein the third and fourth transistors are of the same conductivity type, and wherein the third and fourth control signals are complementary signals with respect to each other.

3. The amplifier circuit of claim 2 , wherein:

the first and third capacitances are different capacitance values;

the second and fourth capacitances are different capacitance values;

the first and third transistors are separately controllable to enable adding of one or both of the first and third capacitances to the first input terminal; and

the second and fourth transistors are separately controllable to enable adding of one or both of the second and fourth capacitances to the second input terminal.

4. The amplifier circuit of claim 3 , wherein the first and third capacitances are binary weighted values, and wherein the second and fourth capacitances are binary weighted values.

5. The amplifier circuit of claim 3 , wherein:

when the first transistor is turned on, the second transistor is not turned on;

when the second transistor is turned on, the first transistor is not turned on;

when the third transistor is turned on, the fourth transistor is not turned on; and

when the fourth transistor is turned on, the third transistor is not turned on.

6. The amplifier circuit of claim 2 , wherein:

the first and third capacitances are equal;

the second and fourth capacitances are equal;

the first and third transistors are separately controllable to enable adding of one or both of the first and third capacitances to the first input terminal; and

the second and fourth transistors are separately controllable to enable adding of one or both of the second and fourth capacitances to the second input terminal.

7. A system comprising:

a processor;

an input device coupled to the processor;

an output device coupled to the processor;

a memory array coupled to the processor; and

a sense amplifier of the memory array, the sense amplifier comprising:

a first compensation capacitor coupled to a first input terminal of the sense amplifier and having a first capacitance;

a second compensation capacitor coupled to a second input terminal of the sense amplifier and having a second capacitance;

a first transistor source-drain coupled between the first compensation capacitor and a reference voltage and having a gate terminal for receiving a first control signal;

a second transistor source-drain coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal; and

a programmable latch circuit arranged to provide the first and second control signals to the first and second transistors, respectively;

wherein the first and second transistors are of the same conductivity type, and wherein the first and second control signals are complementary signals with respect to each other.

8. The system of claim 7 , wherein the sense amplifier comprises:

a third compensation capacitor coupled to the first input terminal of the sense amplifier and having a third capacitance;

a fourth compensation capacitor coupled to the second input terminal of the sense amplifier and having a fourth capacitance;

a third transistor source-drain coupled between the third compensation capacitor and the reference voltage and having a gate terminal for receiving a third control signal; and

a fourth transistor source-drain coupled between the fourth compensation capacitor and the reference voltage and having a gate terminal for receiving a fourth control signal;

wherein the programmable latch circuit is arranged to provide the third and fourth control signals, wherein the third and fourth transistors are of the same conductivity type, and wherein the third and fourth control signals are complementary signals with respect to each other.

9. The system of claim 8 , wherein:

the first and third capacitances are different capacitance values;

the second and fourth capacitances are different capacitance values;

the first and third transistors are separately controllable to enable adding of one or both of the first and third capacitances to the first input terminal of the sense amplifier; and

the second and fourth transistors are separately controllable to enable adding of one or both of the second and fourth capacitances to the second input terminal of the sense amplifier.

10. The system of claim 9 , wherein the first capacitance and the third capacitance differ by a factor of two, and wherein the second capacitance and the fourth capacitance differ by a factor of two.

11. The system of claim 8 , wherein:

when the first control signal has a first state, the first transistor is turned on, and the second control signal has a second state causing the second transistor to be turned off; and

when the third control signal has the first state, the third transistor is turned on, and the fourth control signal has the second state causing the fourth transistor to be turned off.