System and method for providing time offset and frequency offset estimation for vehicle to everything communication system
A method and apparatus are provided. The method includes receiving a reference signal from a transceiver, estimating a time offset (TO) of the reference signal in the frequency domain based on an accumulation of subcarriers before cross-correlation, providing a TO compensated signal of the reference signal based on the estimated TO in the frequency domain, transforming the TO compensated signal into the time domain, and estimating a frequency offset (FO) based on the time domain TO compensated signal.
1. A method, comprising:
receiving a reference signal from a transceiver;
estimating a time offset (TO) of the reference signal in a frequency domain based on a spectral phase ramp introduced by the TO and based on an accumulation of subcarriers before cross-correlation,
compensating the TO of the reference signal based on the estimated TO in the frequency domain by applying the spectral phase ramp to the received reference signal;
providing a TO compensated signal of the reference signal;
transforming the TO compensated signal into a time domain; and
estimating a frequency offset (FO) based on the time domain TO compensated signal.
2. The method of claim 1 , further comprising iteratively updating the FO and the TO.
3. The method of claim 1 , wherein estimating the TO of the reference signal in the frequency domain is further based on a demodulation reference signal (DMRS).
4. The method of claim 1 , wherein the TO is estimated according to:
δ
^
=
N
2
π
1
Δ
δ
angle
(
∑
j
=
0
⌊
M
-
T
δ
-
Δ
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(
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∑
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δ
-
1
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^
(
k
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*
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0
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,
where N is an FFT size, M is a number of allocated subcarriers, T δ is an accumulation length, L δ is a step size and Δ δ is a correlation distance.
5. The method of claim 1 , wherein the TO is compensated according to:
R
_
_
tr
=
D
δ
^
H
R
_
tr
and
D
δ
^
=
(
e
-
j
2
π
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^
N
(
0
)
…
0
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⋱
⋮
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-
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N
(
M
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,
where N is an FFT size, M is a number of allocated subcarriers, {circumflex over (δ)} is the estimated TO and R tr is a truncated received reference signal.
6. The method of claim 1 , wherein the reference signal is received from a transceiver associated with a vehicle to everything (V2X) wireless communication protocol.
7. The method of claim 2 , further comprising compensating the FO in the frequency domain.
8. The method of claim 2 , further comprising compensating the FO in the time domain.
9. The method of claim 3 , wherein estimating the TO of the reference signal in the frequency domain is further based on descrambling the received reference signal according to
Ĥ=diag(S) H R tr , where S is an M×1 matrix of the DMRS signal, M is a number of allocated subcarriers and R tr is an M×1 truncated received vector.
10. The method of claim 7 , wherein iteratively updating the FO and the TO comprises feeding the FO compensated signal back to TO compensation and estimation blocks.
11. The method of claim 8 , further comprising transforming the FO compensated signal into the frequency domain.
12. The method of claim 11 , wherein iteratively updating the FO and the TO comprises feeding the FO compensated signal back to TO compensation and estimation blocks in the frequency domain.
13. An apparatus, comprising:
a memory;
a processor; and
a receiver configured to:
receive a reference signal from a transceiver,
estimate a time offset (TO) of the reference signal in a frequency domain based on a spectral phase ramp introduced by the TO and based on an accumulation of subcarriers before cross-correlation,
compensate the TO of the reference signal based on the estimated TO in the frequency domain by applying the spectral phase ramp to the received reference signal,
provide a TO compensated signal of the reference signal,
transform the TO compensated signal into a time domain, and
estimate a frequency offset (FO) based on the time domain TO compensated signal.
14. The apparatus of claim 13 , wherein the processor is further configured to iteratively update the FO and the TO.
15. The apparatus of claim 13 , wherein estimating the TO of the reference signal in the frequency domain is further based on a demodulation reference signal (DMRS).
16. The apparatus of claim 13 , wherein the reference signal is received from a transceiver associated with a vehicle to everything (V2X) wireless communication protocol.
17. The apparatus of claim 13 , wherein the TO is estimated according to
δ
^
=
N
2
π
1
Δ
δ
angle
(
∑
j
=
0
⌊
M
-
T
δ
-
Δ
δ
L
δ
⌋
(
(
∑
k
=
0
T
δ
-
1
H
^
(
k
+
j
L
δ
)
)
*
*
(
∑
k
=
0
T
δ
-
1
H
^
(
k
+
j
L
δ
+
Δ
δ
)
)
)
)
,
where N is an FFT size, M is a number of allocated subcarriers, T δ is an accumulation length, L δ is a step size and Δ δ is a correlation distance.
18. The apparatus of claim 13 , wherein the TO is compensated according to
R
_
_
tr
=
D
δ
^
H
R
_
tr
and
D
δ
^
=
(
e
-
j
2
π
δ
^
N
(
0
)
…
0
⋮
⋱
⋮
0
…
e
-
j
2
π
δ
^
N
(
M
-
1
)
)
,
where N is an FFT size, M is a number of allocated subcarriers, {circumflex over (δ)} is an estimated TO and R tr is a truncated received reference signal.
19. The apparatus of claim 14 , wherein the processor is further configured to compensate the FO in the frequency domain.
20. The apparatus of claim 14 , wherein the processor is further configured to compensate the FO in the time domain.
21. The apparatus of claim 15 , wherein estimating the TO of the reference signal in the frequency domain is further based on descrambling the received reference signal according to
Ĥ=diag(S) H R tr , where S is an M×1 matrix of the DMRS signal, M is a number of allocated subcarriers and R tr is an M×1 truncated received vector.
22. The apparatus of claim 19 , wherein iteratively updating the FO and the TO comprises feeding the FO compensated signal back to TO compensation and estimation blocks.
23. The apparatus of claim 20 , wherein the processor is further configured to transform the FO compensated signal into the frequency domain.
24. The apparatus of claim 23 , wherein iteratively updating the FO and the TO comprises feeding the FO compensated signal back to TO compensation and estimation blocks in the frequency domain.
25. A method of manufacturing a processor, comprising:
forming the processor as part of a wafer or package that includes at least one other processor, wherein the processor is configured to receive a reference signal from a transceiver,
estimate a time offset (TO) of the reference signal in a frequency domain based on a spectral phase ramp introduced by the TO and based on an accumulation of subcarriers before cross-correlation;
compensate the TO of the reference signal based on the estimated TO in the frequency domain by applying the spectral phase ramp to the received reference signal;
provide a TO compensated signal of the reference signal;
transform the TO compensated signal into a time domain, and estimate a frequency offset (FO) based on the time domain TO compensated signal; and
testing the processor, which includes testing the processor and at least one other processor using one or more electrical to optical converters, one or more optical splitters that split an optical signal into two or more optical signals, and one or more optical to electrical converters.
26. A method of constructing an integrated circuit, comprising:
generating a mask layout for a set of features for a layer of the integrated circuit, wherein the mask layout includes standard cell library macros for one or more circuit features that include a processor configured to receive a reference signal from a transceiver,
estimate a time offset (TO) of the reference signal in a frequency domain based on a spectral phase ramp introduced by the TO and based on an accumulation of subcarriers before cross-correlation,
compensate the TO of the reference signal based on the estimated TO in the frequency domain by applying the spectral phase ramp to the received reference signal,
provide a TO compensated signal of the reference signal,
transform the TO compensated signal into a time domain, and estimate a frequency offset (FO) based on the time domain TO compensated signal; disregarding relative positions of the macros for compliance to layout design rules during the generation of the mask layout;
checking the relative positions of the macros for compliance to layout design rules after generating the mask layout;
upon detection of noncompliance with the layout design rules by any of the macros, modifying the mask layout by modifying each of the noncompliant macros to comply with the layout design rules;
generating a mask according to the modified mask layout with the set of features for the layer of the integrated circuit; and
manufacturing the integrated circuit layer according to the mask.