Multi-metal fill with self-aligned patterning and dielectric with voids
Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
1. A semiconductor fabrication method, comprising:
providing a substrate;
forming a dielectric stack over the substrate;
forming a first metal layer and a second metal layer on the dielectric stack, wherein:
the first and second metal layers comprise different metallic materials from one another; and
a first top surface of the first metal layer is substantially coplanar with a second top surface of the second metal layer:
forming a first metal oxide layer on the first metal layer and a second metal oxide layer on the second metal layer;
forming a first dielectric layer in contact with each side surface of the first and the second metal layers and over the first and second metal oxides layers, wherein the first dielectric layer comprises a void; and
forming a second dielectric layer over the first dielectric layer.
2. The method of claim 1 , further comprising:
forming at least one transistor with one or more contact metal layers over the substrate;
forming an interconnect layer over the one or more contact metal layers;
forming the dielectric stack over the interconnect layer.
3. The method of claim 1 , wherein the forming the first and second metal layers comprises:
forming a first pattern structure and a second pattern structure over the dielectric stack, wherein each of the first and second pattern structures comprises a first spacer, a second spacer, and a center portion between the first and second spacers;
depositing a first metallic material between the first and second pattern structures; and
removing a portion the first metallic material to form the first metal layer, wherein the first top surface of the first metal layer is substantially coplanar with third top surfaces of the first and the second pattern structures.
4. The method of claim 3 , further comprising:
removing the center portion of the second pattern structure between the first and second spacers;
depositing a second metallic material between the first and the second spacers of the second pattern structure; and
removing a portion of the second metallic material to form the second metal layer, wherein the second top surface of the second metal layer is substantially coplanar with fourth top surfaces of the first and the second spacers of the second pattern structure.
5. The method of claim 1 , wherein the metallic materials of the first and second metal layers comprise copper, cobalt, aluminum, or graphene.
6. The method of claim 1 , wherein the forming of the first and the second metal oxide material layers comprises selectively growing aluminum-based oxides, tungsten-based oxides, nickel-based oxides, zirconium-based oxides, or cobalt-based oxides on the first and the second metal layers.
7. The method of claim 1 , wherein the forming the first metal oxide layer on the first metal layer and the second metal oxide layer on the second metal layer comprises:
forming a pattern structure between the first and the second metal layers; and
growing the first oxide layer on the first top surface of the first metal layer; while exposing a third top surface of the pattern structure; and
growing the second metal oxide layer on the second top surface of the second metal layer, while covering the first top surface of the first metal layer with the first metal oxide layer and exposing the third top surface of the pattern structure.
8. A semiconductor fabrication method, comprising:
providing a substrate;
forming a dielectric stack over the substrate; and
forming a first interconnect layer and a second interconnect layer, comprising:
forming a first pattern structure and a second pattern structure over the dielectric stack, wherein each of the first and second pattern structures comprises a first spacer, a second spacer, and a center portion between the first and second spacers;
depositing a first conductive material and a metal oxide layer between the first and second pattern structures to form the first interconnect layer, wherein a bottom surface of the metal oxide layer is above both a first top surface of the first pattern structure and a second top surface of the second pattern structure;
removing the center portion of the second pattern structure between the first and second spacers; and
depositing a second conductive material between the first and second spacers of the second pattern structure to form the second interconnect layer.
9. The method of claim 8 , further comprising:
forming at least one transistor with one or more contact metal layers over the substrate;
forming another interconnect layer over the one or more contact metal layers; and
forming the dielectric stack over the another interconnect layer.
10. The method of claim 8 , wherein the depositing the first conductive material and the metal oxide layer comprises:
forming an opening in the dielectric stack, wherein the opening self-aligns to the first and second pattern structures;
depositing the first conductive material in the opening;
removing a portion of the first conductive material to form a first conductive structure, wherein a third top surface of the first conductive structure is substantially coplanar with both the first top surface of the first pattern structure and the second top surface of the second pattern structure; and
selectively growing the metal oxide layer on the third top surface of the first conductive structure.
11. The method of claim 8 , wherein the depositing the second conductive material comprising:
forming an opening in the dielectric stack, wherein the opening self-aligns to the first and second spacers of the second pattern structure;
depositing the second conductive material in the opening;
removing a portion of the second conductive material to form a second conductive structure, wherein a third top surface of the second conductive structure is substantially coplanar with fourth top surfaces of the first and the second spacers of the second pattern structures, wherein the second conductive material is different from the first conductive material; and
selectively growing an other metal oxide layer on the third top surface of the second conductive structure.
12. The method of claim 8 , further comprising:
forming an opening between the first and second interconnect layers;
disposing a first dielectric layer in the opening, wherein the first dielectric layer comprises a void; and
forming a second dielectric layer over the first dielectric layer.
13. The method of claim 8 , wherein the depositing the second conductive material comprises depositing the second conductive material over the center portion of the first pattern structure.
14. The method of claim 8 , wherein the removing the center portion of the second pattern structure comprises covering the center portion of the first pattern structure with a mask layer.
15. A semiconductor device fabrication method, comprising:
providing a substrate;
forming at least one transistor with one or more contact metal layers over the substrate;
forming an interconnect layer over the one or more contact metal layers;
forming a first and a second plurality of pattern structures over the interconnect layer;
forming a first conductive layer between each of the first and the second plurality of pattern structures;
masking the second plurality of pattern structures;
forming an opening in each of the first plurality of pattern structures while the second plurality of pattern structures are masked; and
forming a second conductive layer in the opening of each of the first plurality of pattern structures.
16. The method of claim 15 , wherein the forming the first and the second plurality of pattern structures over the interconnect layer comprises:
forming a dielectric stack over the interconnect layer;
forming a plurality of hard-mask structures over the dielectric stack; and
forming spacers adjacent to each of the plurality of hard-mask structures.
17. The method of claim 15 , wherein the forming the opening in each of the first plurality of pattern structures comprises:
forming spacers adjacent to each of the first and the second plurality of pattern structures;
exposing the first plurality of pattern structures while the second plurality of pattern structures are masked; and
selectively removing the first plurality of pattern structures from the spacers adjacent to each of the first plurality of pattern structures.
18. The method of claim 15 , wherein the forming the first and the second conductive layers comprises:
depositing a first conductive material between each of the first and the second plurality of pattern structures and a second conductive material in the opening of each of the first plurality of pattern structures; and
removing a portion of the second conductive material to level with the first conductive material.
19. The method of claim 15 , further comprising forming first and second metal oxides over the first and second conductive layers, respectively, via a chemical vapor deposition (CVD), physical vapor deposition (PVD), or a spin-on process.
20. The method of claim 15 , further comprising:
removing the second plurality of pattern structures;
forming a first dielectric layer between the first and the second conductive layers; and
forming a second dielectric layer over the first dielectric layer and the first and the second conductive layers.