SEMICONDUCTOR DEVICES, CIRCUITS AND METHODS FOR READ AND/OR WRITE ASSIST OF AN SRAM CIRCUIT PORTION BASED ON VOLTAGE DETECTION AND/OR TEMPERATURE DETECTION CIRCUITS
A method of operating a semiconductor device powered by a first power supply potential can include: generating an assist signal with an enable logic level in response to a voltage window detection circuit indicating the first power supply potential is in a first voltage window at a lower end of an operating range of the semiconductor device and generating the assist signal with a disable logic level in response to the voltage window detection circuit indicating the first power supply potential is in a second voltage window at an upper end of the operating range of the semiconductor device. Read or write operations to an SRAM can have improved reliability when the assist signal has the enable logic level.
1 . A method of operating a semiconductor device that is powered by a first power supply potential, including:
generating at least one assist signal having an assist enable logic level in response to a voltage window detection circuit indicating the first power supply potential is in a first voltage window, the first voltage window being a voltage window at a lower end of an operating range of the semiconductor device and generating the at least one assist signal having an assist disable logic level in response to the voltage window detection circuit indicating the first power supply potential is in a second voltage window, the second voltage window being a voltage window at an upper end of the operating range of the semiconductor device and a read operation or a write operation to a static random access memory (SRAM) cell has an improved reliability when the at least one assist signal has the assist enable logic level as compared to when the at least one assist signal does not have the assist enable logic level.
2 . The method of claim 1 , further including:
generating the at least one assist signal having the assist enable logic level in response to a temperature window detection circuit indicating the temperature of the semiconductor device is in a first temperature window and the voltage window detection circuit indicates that the first power supply potential is in a third voltage window, the first temperature window being at one end of an allowable operating temperature range of the semiconductor device, the third voltage window is between the first voltage window and the second voltage window, and generating the at least one assist signal having the assist disable logic level when the voltage window detection circuit indicates the first power supply potential is in the third voltage window and the temperature window detection circuit indicates the temperature of the semiconductor device is between the first temperature window and another end of the allowable operating temperature range of the semiconductor device.
3 . The method of claim 2 , wherein:
the one end is an upper temperature end of the operating temperature range of the semiconductor device.
4 . The method of claim 2 , wherein:
the one end is a lower temperature end of the operating temperature range of the semiconductor device.
5 . The method of claim 1 , wherein:
the at least one assist signal includes a read assist.
6 . The method of claim 5 , further including:
generating a word line potential that is less than the first power supply potential in response to the read assist signal; wherein
the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the read operation.
7 . The method of claim 6 , wherein:
the step of generating the word line potential includes generating the word line potential that is less than the first power supply potential in response to the read assist signal and a read signal, the read signal indicates that data from the SRAM cell is to be accessed.
8 . The method of claim 6 , wherein:
the step of generating the word line potential includes generating the word line potential that is less than the first power supply potential when the read assist signal has the assist enable logic level and generating the word line potential that is essentially the same potential as the first power supply potential when the read assist signal has the assist disable logic level.
9 . The method of claim 5 , further including:
enabling a threshold voltage compensation circuit in response to the read assist signal, the threshold voltage compensation circuit is included in a sense amplifier circuit and compensates for differences in threshold voltages in a first insulated gate field effect transistor (IGFET) and a second IGFET during a read operation of data from the SRAM cell.
10 . The method of claim 9 , wherein:
the step of enabling a threshold voltage compensation circuit includes enabling the threshold voltage compensation circuit when the read assist signal has the assist enable logic level and disabling the threshold voltage compensation circuit when the read assist signal has the assist disable logic level.
11 . The method of claim 1 , wherein:
the at least one assist signal includes a write assist signal.
12 . The method of claim 1 , further including the step of:
generating a write potential that is less than a reference potential in response to the write assist signal; wherein the first power supply potential provides an upper power rail to the semiconductor device and the reference potential provides a lower power rail to the semiconductor device, a first bit line and a second bit line are connected to the SRAM cell, and essentially the write potential is driven to one of the first or the second bit lines during the write operation.
13 . The method of claim 12 , wherein:
the step of generating the write potential includes generating the write potential that is less than the reference potential when the write assist signal has the assist enable logic level and generating the write potential that is essentially the reference potential when the write assist signal has the assist disable logic level.
14 . The package of claim 11 , further including:
generating a word line potential that is greater than the first power supply potential in response to the write assist signal; wherein the SRAM cell is coupled to receive the word line potential at a gate terminal of an insulated gate field effect transistor (IGFET) during the write operation.
15 . The method of claim 14 , wherein:
the step of generating the word line potential includes generating the word line potential that is greater than the first power supply potential when the write assist signal has the assist enable logic level and generating the word line potential that is essentially the same potential as the first power supply potential when the write assist signal has the assist disable logic level.
16 . The method of claim 11 , further including the step of:
generating a cell power supply potential that is less than the first power supply potential in response to the write assist signal; wherein the SRAM cell is coupled to receive, and is powered by, the cell power supply potential.
17 . The method of claim 16 , wherein:
the step of generating the cell power supply potential includes generating the cell power supply potential that is less than the first power supply potential when the write assist signal has the assist enable logic level and generating the cell power supply potential that is essentially the same potential as the first power supply potential when the write assist signal has the assist disable logic level.
18 . The method of claim 16 , wherein:
the step of generating the cell power supply potential includes generating the cell power supply potential that is less than the first power supply potential in response to the write assist signal and a write signal, the write signal indicates that data is to be written to the SRAM cell.
19 . The method of claim 1 , wherein:
the semiconductor device includes a processor circuit portion and a SRAM circuit portion, the processor circuit portion and the SRAM circuit portion are commonly powered by the first power supply potential, the SRAM circuit portion includes the SRAM cell.
20 . The method of claim 19 , wherein:
the processor circuit portion and the SRAM circuit portion are connected by a bus for carrying data between the processor circuit portion and the SRAM circuit portion.