IP Library Assignment 049987/0361
Patent Assignment
Reel/Frame 049987/0361

Assignment of Assignor's Interest

Recorded: 2019-08-07 Pages: 9
Assignor
WALKER, DARRYL G.
Executed: 2019-08-05
Assignee
SAMSUNG ELECTRONICS CO., LTD.
129, SAMSUNG-RO, YEONGTONG-GU, SUWON-SI, GYEONGGI-DO, 16677, KOREA, REPUBLIC OF
Covered Properties (51)
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Voltage Detection and/or Temperature Detection Circuits
Semiconductor Device Having Temperature Sensor Circuit That Detects a Temperature Range Upper Limit Value and a Temperature Range Lower Limit Value
Patent: 9,772,232 →
Application: 14/265,642 →
Publication: US 2015/0276500
Power Up of Semiconductor Device Having a Temperature Circuit and Method Therefor
Patent: 9,194,754 →
Application: 14/265,653 →
Publication: US 2015/0276501
Semiconductor Device Having Subthreshold Operating Circuits Including a Back Body Bias Potential Based on Temperature Range
Patent: 9,939,330 →
Application: 14/265,668 →
Publication: US 2015/0280702
Semiconductor Device Having a Temperature Circuit That Provides a Plurality of Temperature Operating Ranges
Patent: 9,810,585 →
Application: 14/265,682 →
Publication: US 2015/0276510
Ssemiconductor Device Having Temperature Sensor Circuits
Patent: 9,274,007 →
Application: 14/265,729 →
Publication: US 2015/0276502
Semiconductor Device Including Temperature Ranges Having Temperature Thresholds and Method of Determining Therefor
Application: 14/484,529 →
Publication: US 2016/0054374
Testing and Setting Performance Parameters in a Semiconductor Device and Method Therefor
Application: 14/484,546 →
Publication: US 2016/0054377
Testing and Setting Performance Parameters in a Semiconductor Device and Method Therefor
Application: 14/484,575 →
Publication: US 2016/0054378
Testing and Setting Performance Parameters in a Semiconductor Device and Method Therefor
Patent: 9,645,191 →
Application: 14/484,593 →
Publication: US 2016/0054379
Testing and Setting Performance Parameters in a Semiconductor Device and Method Therefor
Patent: 9,658,277 →
Application: 14/484,620 →
Publication: US 2016/0054380
Multi-Chip Non-Volatile Semiconductor Memory Package Including Heater and Sensor Elements
Patent: 9,613,719 →
Application: 14/639,270 →
Multi-Chip Non-Volatile Semiconductor Memory Package Including Heater and Sensor Elements
Application: 14/639,301 →
Multi-Chip Non-Volatile Semiconductor Memory Package Including Heater and Sensor Elements
Patent: 9,928,925 →
Application: 14/639,313 →
Multi-Chip Non-Volatile Semiconductor Memory Package Including Heater and Sensor Elements
Patent: 9,286,991 →
Application: 14/639,325 →
Package Including a Plurality of Stacked Semiconductor Devices Including a Capacitance Enhanced Through via and Method of Manufacture
Patent: 9,378,778 →
Application: 14/755,157 →
Package Including a Plurality of Stacked Semiconductor Devices Including a Capacitance Enhanced Through via and Method of Manufacture
Patent: 9,455,189 →
Application: 14/755,193 →
Power Up of Semiconductor Device Having a Temperature Circuit and Method Therefor
Patent: 9,933,317 →
Application: 14/938,433 →
Publication: US 2016/0064064
Semiconductor Device Having Temperature Sensor Circuits
Patent: 9,631,982 →
Application: 15/049,472 →
Publication: US 2016/0169750
Multi-Chip Non-Volatile Semiconductor Memory Package Including Heater and Sensor Elements
Patent: 9,548,126 →
Application: 15/057,959 →
Package Including a Plurality of Stacked Semiconductor Devices Including a Capacitance Enhanced Through via and Method of Manufacture
Patent: 9,431,088 →
Application: 15/161,468 →
Package Including a Plurality of Stacked Semiconductor Devices Including a Capacitance Enhanced Through via and Method of Manufacture
Patent: 9,508,692 →
Application: 15/245,563 →
Package Including a Plurality of Stacked Semiconductor Devices Having Area Efficient Esd Protection
Patent: 9,711,500 →
Application: 15/259,693 →
Package Including a Plurality of Stacked Semiconductor Devices Having Area Efficient Esd Protection
Application: 15/259,735 →
Package Including a Plurality of Stacked Semiconductor Devices Having Area Efficient Esd Protection
Application: 15/259,759 →
Package Including a Plurality of Stacked Semiconductor Devices Including a Capacitance Enhanced Through via and Method of Manufacture
Patent: 9,607,969 →
Application: 15/357,829 →
Package Including a Plurality of Stacked Semiconductor Devices Including a Capacitance Enhanced Through via and Method of Manufacture
Patent: 9,685,427 →
Application: 15/469,448 →
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Voltage Detection and/or Temperature Detection Circuits
Application: 15/587,901 →
Publication: US 2017/0372773
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Power Supply Voltage Detection Circuits
Application: 15/587,911 →
Publication: US 2017/0372774
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Voltage Detection and/or Temperature Detection Circuits
Application: 15/587,923 →
Publication: US 2017/0372775
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Voltage Detection and/or Temperature Detection Circuits
Application: 15/587,938 →
Publication: US 2017/0372776
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Voltage Detection and/or Temperature Detection Circuits
Patent: 9,940,999 →
Application: 15/587,947 →
Publication: US 2017/0372777
Package Including a Plurality of Stacked Semiconductor Devices Including a Capacitance Enhanced Through via and Method of Manufacture
Patent: 9,842,830 →
Application: 15/626,534 →
Testing a Semiconductor Device Including a Voltage Detection Circuit and Temperature Detection Circuit That Can Be Used to Generate Read Assist and/or Write Assist in an Sram Circuit Portion and Method Therefor
Application: 15/628,589 →
Publication: US 2017/0372793
Testing a Semiconductor Device Including a Voltage Detection Circuit and Temperature Detection Circuit That Can Be Used to Generate Read Assist and/or Write Assist in an Sram Circuit Portion and Method Therefor
Application: 15/628,593 →
Publication: US 2017/0372794
Package Including a Plurality of Stacked Semiconductor Devices Having Area Efficient Esd Protection
Patent: 9,997,513 →
Application: 15/645,196 →
Semiconductor Device Having Temperature Sensor Circuit That Detects a Temperature Range Upper Limit Value and a Temperature Range Lower Limit Value
Patent: 9,958,341 →
Application: 15/713,643 →
Publication: US 2018/0010968
Semiconductor Device Having Temperature Circuit That Sets Temperature Ranges and Is Disabled Upon Power Supply Transition
Application: 15/804,944 →
Publication: US 2018/0058944
Package Including a Plurality of Stacked Semiconductor Devices an Interposer and Interface Connections
Patent: 9,929,127 →
Application: 15/836,851 →
Package Including a Plurality of Stacked Semiconductor Devices, an Interposer and Interface Connections
Application: 15/934,183 →
Semiconductor Device Having Temperature Sensor Circuit That Detects a Temperature Range Upper Limit Value and a Temperature Range Lower Limit Value
Application: 15/948,919 →
Publication: US 2018/0231421
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Voltage Detection and/or Temperature Detection Circuits
Application: 15/948,928 →
Publication: US 2018/0233195
Semiconductor Memory Device and Method Having Temperature Sensing Circuit and Count Value for Adjusting Circuit Operations
Application: 15/965,893 →
Publication: US 2018/0245989
Package Including a Plurality of Stacked Semiconductor Devices Having Area Efficient Esd Protection
Application: 16/002,183 →
Testing and Setting Performance Parameters in a Semiconductor Device and Method Therefor
Application: 16/017,217 →
Publication: US 2018/0306854
Package Including a Plurality of Stacked Semiconductor Devices, an Interposer and Interface Connections
Application: 16/130,962 →
Package Including a Plurality of Stacked Semiconductor Devices, an Interposer and Interface Connections
Application: 16/132,409 →
Semiconductor Devices, Circuits and Methods for Read and/or Write Assist of an Sram Circuit Portion Based on Voltage Detection and/or Temperature Detection Circuits
Application: 16/172,787 →
Publication: US 2019/0074055
Testing a Semiconductor Device Including a Voltage Detection Circuit and Temperature Detection Circuit That Can Be Used to Generate Read Assist and/or Write Assist in an Sram Circuit Portion and Method Therefor
Application: 16/231,303 →
Publication: US 2019/0130988
Package Including a Plurality of Stacked Semiconductor Devices, an Interposer and Interface Connections
Application: 16/238,760 →
Package Including a Plurality of Stacked Semiconductor Devices, an Interposer and Interface Connections
Application: 16/382,545 →